CTNF 19/062,294 CTNF 91055 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-4 rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-4 of U.S. Patent No. 12,260,101 . Although the claims at issue are not identical, they are not patentably distinct from each other because of the following analysis: Instant application 19/062,294 U.S. Patent 12,260,101 1. An apparatus, comprising: an array of memory cells including a first block, a second block, a third block, and a fourth block of single level memory cells and a first block of quad level memory cells; and a controller coupled to the array of memory cells, wherein the controller is configured to: update a read source for a first read request for a first portion of data to a first block of quad level memory cells in response to an amount of a second portion of data written to the second block of single level memory cells being at least a threshold amount. 1. An apparatus, comprising: an array of memory cells; a controller coupled to the array of memory cells, wherein the controller is configured to determine a source for read requests and to: direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount; and direct read requests for the first portion of data to a first block of a quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount. 2. The apparatus of claim 1, wherein the controller is configured to update the read source for the first read request for the first portion of data to the first block of quad level memory cells in response to a write operation writing the first portion of data to the first block of quad level memory cells being complete. 1. An apparatus, comprising: an array of memory cells; a controller coupled to the array of memory cells, wherein the controller is configured to determine a source for read requests and to: direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount; and direct read requests for the first portion of data to a first block of a quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount. 3. The apparatus of claim 1, wherein the controller is configured to update a read source for a second read request for a second portion of data to the first block of quad level memory cells in response to an amount of a third portion of data written to the third block of single level memory cells being at least the threshold amount. 3. The apparatus of claim 1, direct read requests for a second portion of data to a second block of single level memory cells in response to an amount of a third portion of data written to a third block of single level memory cells being less than the threshold amount. 4. The apparatus of claim 1, wherein the controller is configured to update the read source for the second read request for the second portion of data to the first block of quad level memory cells in response to a write operation writing the second portion of data to the first block of quad level memory cells being complete. 4. The apparatus of claim 3, direct read requests for the second portion of data to a first block of a quad level memory cells in response to the amount of the third portion of data written to the third block of single level memory cells being at least the threshold amount . Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-12 AIA Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: “write a first portion of a data to a first single level block and a first portion of a quad level block”. The claim language does not indicate the read source of the first portion of data. Claims 9 and 15 appear to include the write operation steps. Thus, the claim renders indefinite since it is illogical to update or switching from an original source to a secondary source without knowing the original source, or whether the data was even written in the source. Appropriate correction is required . Claims 2-8, depend on claim 1, and are rejected under same ground for failing to cure the deficiency of claim 1 . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 9-15 are allowed. 13-03 AIA The following is an examiner’s statement of reasons for allowance: The prior art of records: Shah et al (U.S. 2023/0197176) discloses a system and method for data protection during power loss, which includes detecting power loss during process of programming QLC memory in the system, storing unprogrammed data in a SLC memory to be used for reconstructing data prior to powering down the system, or after the system is powered back up. Inbar et al (U.S. 2021/0241819) disclose a technique to improve foggy-fine programming by foggy write data to QLC in parallel with initial writing of the data to SLC using same buffer. Loh et al (U.S. 2014/0143493) discloses bypassing a cache if memory request is from a predetermined class of memory requests, such as instruction, or a texture. However, the prior art of record, alone or in combination, does not teach the claimed limitation in claims 9-15. Thus, examiner cannot reasonably combine the prior art in the manner claimed . Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shah et al (U.S. 2023/0197176) discloses a system and method for data protection during power loss, which includes detecting power loss during process of programming QLC memory in the system, storing unprogrammed data in a SLC memory to be used for reconstructing data prior to powering down the system, or after the system is powered back up. Inbar et al (U.S. 2021/0241819) disclose a technique to improve foggy-fine programming by foggy write data to QLC in parallel with initial writing of the data to SLC using same buffer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHOA D DOAN whose telephone number is (571)272-5950. The examiner can normally be reached Mon-Fri 1000-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHOA D DOAN/Primary Examiner, Art Unit 2133 Application/Control Number: 19/062,294 Page 2 Art Unit: 2133 Application/Control Number: 19/062,294 Page 3 Art Unit: 2133 Application/Control Number: 19/062,294 Page 4 Art Unit: 2133 Application/Control Number: 19/062,294 Page 5 Art Unit: 2133 Application/Control Number: 19/062,294 Page 6 Art Unit: 2133 Application/Control Number: 19/062,294 Page 7 Art Unit: 2133 Application/Control Number: 19/062,294 Page 8 Art Unit: 2133 Application/Control Number: 19/062,294 Page 9 Art Unit: 2133 Application/Control Number: 19/062,294 Page 10 Art Unit: 2133 Application/Control Number: 19/062,294 Page 11 Art Unit: 2133 Application/Control Number: 19/062,294 Page 12 Art Unit: 2133 Application/Control Number: 19/062,294 Page 13 Art Unit: 2133
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