DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 41-43, 46-47, 51-53, 56-57 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6-7, 11-13, 16-17 of the 16/879,991 Patent (US 12,254,527 B2). Although the claims at issue are not identical, they are not patentably distinct because they claim substantially the same subject matter, as explained below.
Claim 41 is determined to be obvious in light of claim 1 of 16/879,991 (now is US patent US 12,254,527 B2) based on reasons below for having similar limitations.
Instant application claim 41
16/879,991 Patent claim 1
41. An apparatus, comprising: a plurality of shared resources comprising: a plurality of programmable processing cores; and a plurality of fixed-function hardware units
1.An apparatus, comprising: a plurality of shared resources comprising: a plurality of programmable processing cores configured to process graphics primitives and corresponding data; and a plurality of fixed-function hardware units
wherein the shared resources are configured to implement a configurable number of virtual pipelines, wherein each virtual pipeline is configured to execute commands stored in at least one buffer
wherein the shared resources are allocated to implement a configurable number of virtual graphics pipelines, wherein the virtual graphics pipelines are to concurrently execute commands that are fed to each virtual graphics pipeline using at least one buffer
wherein each virtual pipeline is associated with a configurable memory allocation, including the at least one buffer, in a memory hierarchy
each virtual graphics pipeline includes a number of shared resources dynamically configurable in response to at least one of a system event or user input; each virtual graphics pipeline is mapped to memory hierarchy resources of the apparatus based on a mapping that is dynamically adjustable in response to one or more of at least one of system event or at least one user input; and the virtual graphics pipelines are reconfigured in response to one or more at least one system event or at least one user input.
Claim 1 of the 16/879,991 Patent discloses every limitation recited in instant claim 41 and more. Claim 1 requires shared resources comprising programmable processing cores and fixed-function hardware units allocated to a configurable number of virtual (graphics) pipelines that execute commands using at least one buffer, each mapped to memory hierarchy resources — which is the identical arrangement recited generically in claim 41, except claim 41 removes the "graphics" qualifier and the dynamic-adjustment/reconfiguration limitations, making claim 41 the broader claim. A species (parent claim 1) that discloses dynamically-mapped, reconfigurable virtual graphics pipelines necessarily discloses the broader genus recited in claim 41 (virtual pipelines with a static or dynamic memory allocation), so instant claim 41 is anticipated by, or at minimum would have been an obvious broadening variant of, claim 1 of the 16/879,991 Patent.
Claim 42 is determined to be obvious in light of claim 2 of 16/879,991 (now is US patent US 12,254,527 B2) based on reasons below for having similar limitations.
Instant application claim 42
16/879,991 Patent claim 2
42. (New) The apparatus of claim 41, further comprising: a command processor configured to retrieve commands from the at least one buffer associated with one of the virtual pipelines and dispatch the commands for execution by a corresponding virtual pipeline.
2. The apparatus of claim 1, further comprising: a command processor configured to schedule and dispatch commands to a configurable number of queues, wherein the configurable number of queues are configured to store packets comprising the commands.
Claim 2 of the 16/879,991 Patent discloses a command processor that schedules and dispatches commands stored in queues to the virtual pipelines, which is the same function recited in claim 42 using the term "buffer" instead of "queue." Retrieving from a buffer and dispatching to a corresponding pipeline is not patentably distinct from scheduling/dispatching commands stored in a queue to a pipeline, since a buffer and a queue perform an interchangeable command-storage function in this context.
Claim 43 is determined to be obvious in light of claim 3 of 16/879,991 (now is US patent US 12,254,527 B2) based on reasons below for having similar limitations.
Instant application claim 43
16/879,991 Patent claims 3
43. (New) The apparatus of claim 42, wherein each virtual pipeline is associated with a respective buffer, and each respective buffer includes at least commands for execution by the
associated virtual pipeline.
3. The apparatus of claim 2, further comprising: an application driver configured to allocate memory for the queues.
Claims 3 of the 16/879,991 Patent already disclose a per-pipeline queue storing commands with allocated memory, which is not patentably distinct from a per-pipeline "respective buffer" storing commands as recited in claim 43; buffer and queue are used interchangeably for command storage in this art.
Claim 46 is determined to be obvious in light of claim 5 of 16/879,991 (now is US patent US 12,254,527 B2) based on reasons below for having similar limitations.
Instant application claim 46
16/879,991 Patent claim 5
46. (New) The apparatus of claim 41, wherein the apparatus is configured to allocate at least a subset of the plurality of shared resources to the configurable number of virtual pipelines.
5. The apparatus of claim 4, further comprising: a control unit configured to allocate the plurality of shared resources to the configurable number of virtual graphics pipelines.
Claim 5 discloses the identical resource-allocation function; reciting the "apparatus" generally rather than a specific "control unit" performing the allocation is not a patentable distinction.
Claim 47 is determined to be obvious in light of claim 7 of 16/879,991 (now is US patent US 12,254,527 B2) based on reasons below for having similar limitations.
Instant application claim 47
16/879,991 Patent claim 7
47. (New) The apparatus of claim 41, wherein the apparatus is configured to dynamically modify a configurable number of virtual pipeline stages within each virtual pipeline of the configurable number of virtual pipelines.
7. The apparatus of claim 6, wherein each virtual graphics pipeline comprises a configurable number of virtual graphics pipe stages configured to execute commands using the shared resources; and the control unit is configured to modify the configurable number of virtual graphics pipe stages.
Claim 7 discloses modifying the configurable number of pipeline stages within each pipeline, the same function claimed generically in claim 47.
Claims 51-53, 56-57, they recite limitations similar in scope to the limitations of Claims 41-43, 46-47 but as a method which determined to be obvious in light of claim 1-3, 6-7 of 16/879,991 (now is US patent US 12,254,527 B2) which recite limitations similar in scope to the limitations of Claims 11-13, 16-17 of 16/879,991 (now is US patent US 12,254,527 B2) based on same reason described above for having similar limitations as described above for Claims 41-43, 46-47.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 53 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 53 recite the limitation "at least one buffer" in page 4, lines 8-9. Claim 53 which depends on Claim 51 already recites "each virtual pipeline is associated with a configurable memory allocation, including at least one buffer, in a memory hierarchy”. It is unclear Claim 53 “at least one buffer” whether this is: (i) the same "at least one buffer" already introduced in claim 51 (in which case it should read "the at least one buffer"), or (ii) an additional buffer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 41-42, 44-47, 49-50, 51-52, 54-57, 59-60 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johnson (US 20180089881 A1), in view of McCrary et al. (US 20020023118 A1. Hereinafter McCrary).
Regarding Claim 41, Johnson teaches an apparatus, comprising: a plurality of shared resources (Johnson, Paragraph [0056], "The graphics core array 414 couples with shared function logic 420 that includes multiple resources that are shared between the graphics cores in the graphics core array."); comprising: a plurality of programmable processing cores (Johnson, Paragraph [0059], "each execution unit (e.g. 608A) is a stand-alone programmable general purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A-608N is scalable to include any number individual execution"); and a plurality of fixed-function hardware units (Johnson, Paragraph [0046], "The 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system 315."); (Johnson, Paragraph [0047], "media pipeline 316 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration"), wherein the shared resources are configured to implement a configurable number of virtual pipelines (Johnson, Paragraph [0131], "multiple GPUs 1531-1532 in the host physical machine are efficiently shared between VMs 1501-1502 using a virtualization software 1510"); (Johnson, Paragraph [0134], "exposing a virtual GPU (VGPU) <read on virtual pipeline> to the guest OS"); (Johnson, Paragraph [0140], "the virtualization software 1510 uses some number of host GPUs 1531-1532 to share with guests"), wherein each virtual pipeline is configured to execute commands stored in at least one buffer (Johnson, Paragraph [0136], "the GPU scheduler 1520 may generate a FIFO of work items 1622-1623 for each GPU 1530-1531, respectively. Each GPU 1530-1531 will then read commands from its respective FIFO buffer 1622-1623, respectively."), [[wherein each virtual pipeline is associated with a configurable memory allocation, including the at least one buffer]], in a memory hierarchy (Johnson, Paragraph [0036], "The internal cache units 204A-204N and shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache").
But Johnson does not explicitly disclose, at the per-virtual-pipeline granularity, that each virtual pipeline is associated with a configurable memory allocation, including the at least one buffer.
However, McCrary teaches each virtual pipeline is associated with a configurable memory allocation, including the at least one buffer (McCrary, Paragraph [0049], "the control system additionally comprises one or more input memory buffers respectively intended for said one or more of the shared resources, for gathering and queuing subcommands to be input to the shared resource"); (McCrary, Paragraph [0061], "Each of the shared resources is provided with two buffers for queuing. For the shared resource 18, there are an input buffer 24 serving for subcommands queue, and an output buffer 26 serving for responses queue.").
McCrary and Johnson are analogous since both address the problem of efficient dispatch and execution of commands using shared processing resources. Johnson provided a way of virtualizing physical GPU resources into virtualized pipelines fed by FIFO command buffers in a memory hierarchy that is dynamically allocated by the host driver/scheduler. McCrary provided a way of giving each shared resource its own dedicated input memory buffer so commands directed to that resource can be queued, prioritized, and executed independently of other resources. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate per-shared-resource input buffer arrangement taught by McCrary into the modified invention of Johnson such that each virtualized pipeline of multi-GPU virtualization architecture is associated with its own configurable, per-pipeline command buffer allocation within the host memory hierarchy. The motivation is to achieve parallel, non-blocking utilization of the shared resources so that each resource is not locked for the entire duration of a command and different pipelines can be fed independently, as discussed by McCrary in Paragraph [0063].
Regarding Claim 42, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches further comprising: a command processor configured to retrieve commands from the at least one buffer associated with one of the virtual pipelines and dispatch the commands for execution by a corresponding virtual pipeline (Johnson, Paragraph [0139], "The host KMD 1513 or GPU scheduler 1520 <read on command processor> receives command buffers from each VMX process 1518 or from the guest OS directly."); (Johnson, Paragraph [0143], "the host KMD 1513 or GPU scheduler 1520 may decode and queue up command buffers to a specific GPU in the multi-GPU environment"); (Johnson, Paragraph [0136], "Each GPU 1530-1531 will then read commands from its respective FIFO buffer 1622-1623, respectively.").
Regarding Claim 43, the combination of Johnson and McCrary teaches the invention in Claim 42.
The combination further teaches wherein: each virtual pipeline is associated with a respective buffer, and each respective buffer includes at least commands for execution by the associated virtual pipeline (Johnson, Paragraph [0136], "the GPU scheduler 1520 may generate a FIFO of work items 1622-1623 for each GPU 1530-1531, respectively. Each GPU 1530-1531 will then read commands from its respective FIFO buffer 1622-1623, respectively.").
Regarding Claim 44, the combination of Johnson and McCrary teaches the invention in Claim 42.
The combination further teaches wherein: the command processor is configured to retrieve commands from the at least one buffer associated with one of the virtual pipelines and dispatch the commands for execution by the corresponding virtual pipeline (Johnson, Paragraph [0143], "the host KMD 1513 or GPU scheduler 1520 may decode and queue up command buffers to a specific GPU"), [[based on priority]]. But Johnson does not explicitly disclose dispatching based on priority.
However, McCrary teaches based on priority (McCrary, Paragraph [0021], "assigning priorities to said subcommands"); (McCrary, Paragraph [0051], "the input memory buffers are capable of sorting the subcommands in the queue so that the first subcommand to be read from the queue is always that having the highest priority in the queue.").
McCrary and Johnson are analogous since both direct commands from a controller to shared resources via buffers. Johnson provided a way of lists priority scheduling as a preemption option. McCrary provided a way of supplies the concrete priority-based read-out mechanism from per-resource input buffers. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate priority-based read-out taught by McCrary into the modified invention of Johnson such that system can achieve the goal of executing urgent operations ahead of less-urgent ones
Regarding Claim 45, the combination of Johnson and McCrary teaches the invention in Claim 42.
The combination further teaches wherein: the command processor is configured to retrieve commands from the at least one buffer associated with one of the virtual pipelines and dispatch the commands for execution by the corresponding virtual pipeline based on detected activity information (Johnson, Paragraph [0147], "a bit vector may be written into the shared memory area where each bit indicates whether an engine in the GPU 1530 is busy (1) or idle (0)... This information can be used by the host KMD 1513 or GPU scheduler 1520 to submit command buffers of specific types from different guests.").
Regarding Claim 46, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches wherein: the apparatus is configured to allocate at least a subset of the plurality of shared resources to the configurable number of virtual pipelines (Johnson, Paragraph [0132], "There may be no fixed allocations of GPU resources because the GPU scheduler or KMD host software determines the GPU resources dynamically as needed."); (Johnson, Paragraph [0140], "the virtualization software 1510 uses some number of host GPUs 1531-1532 to share with guests and there may be GPUs in the host not shared with any guests.").
Regarding Claim 47, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches wherein: the apparatus is configured to dynamically modify a configurable number of virtual pipeline stages within each virtual pipeline of the configurable number of virtual pipelines (Johnson, Paragraph [0055], "graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed."); (Johnson, Paragraph [0085], "geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.").
Regarding Claim 49, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches wherein: the configurable number of virtual pipelines includes at least one virtual pipeline configured for graphics commands (Johnson, Paragraph [0046], "GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images"), and at least one virtual pipeline configured for compute commands (Johnson, Paragraph [0053], "the execution units additionally include general-purpose logic that is programmable to perform parallel general purpose computational operations, in addition to graphics processing operations."); (Johnson, Paragraph [0052], "the 3D pipeline 312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs").
Regarding Claim 50, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches wherein: the plurality of shared resources are configurable to concurrently execute the commands in the configurable number of virtual pipelines (Johnson, Paragraph [0147], "if GPU 1531 is busy running a video decode task and the GPU hardware is designed to allow full execution overlap, then the bit vector for that GPU would indicate that the video decode engine is busy but other engines are idle and the scheduler 1520 can therefore submit command buffers for 3D rendering or BLIT operations to the same GPU 1531 (e.g., using a different execution engine within the same GPU hardware).").
Regarding Claim 51, it recites limitations similar in scope to the limitations of Claim 41 but as a method and the combination of Johnson and McCrary teaches all the limitations as of Claim 41. Therefore is rejected under the same rationale.
Regarding Claim 52, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 54, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 55, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 56, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 57, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 59, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Regarding Claim 60, it recites limitations similar in scope to the limitations of Claim 42 and therefore is rejected under the same rationale.
Claim(s) 43, 53 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johnson (US 20180089881 A1), in view of McCrary et al. (US 20020023118 A1. Hereinafter McCrary) as applied to Claim 41, 51 above respectively and further in view of Yoo et al. (US 20160189332 A1, hereinafter Yoo).
Regarding Claim 43, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches wherein: each virtual pipeline is associated with a respective buffer (Johnson, Paragraph [0136], "the GPU scheduler 1520 may generate a FIFO of work items 1622-1623 for each GPU 1530-1531, respectively.").
But Johnson does not explicitly disclose that each virtual pipeline (as opposed to each physical GPU) is associated with a respective buffer, and each respective buffer includes at least commands for execution by the associated virtual pipeline.
However, Yoo teaches each virtual pipeline is associated with a respective buffer (Yoo, Paragraph [0076], "The vGPU 420 <read on virtual pipeline> according to an example embodiment may include a virtual buffer (vbuffer) 421 and a shadow buffer (sbuffer) 423 as command buffers."); and each respective buffer includes at least commands for execution by the associated virtual pipeline (Yoo, Paragraph [0068], "the vGPU monitoring unit 250 may monitor a command buffer of the first vGPU to determine whether the amount of data of the command stored in the command buffer is equal to or greater than the predetermined threshold."); (Yoo, Paragraph [0051], "The vGPUs 121, 123, and 125 according to an example embodiment may respectively receive commands from the OSs 111, 113, and 115.").
Yoo and Johnson are analogous since both concern virtualized GPU architectures in which multiple virtualized GPU instances share underlying physical GPU resources and consume commands sourced from higher-level software (guest OS / VM). Johnson provided a way of virtualizing physical GPU hardware into multiple pipelines fed by scheduler-managed FIFO command buffers. Yoo provided a way of attaching an individual command buffer (vbuffer/sbuffer ring buffers) to each vGPU so commands for a given vGPU are stored in that vGPU's own buffer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yoo’s per-vGPU command buffer teaching into the modified invention of Johnson such that each virtualized pipeline in Yoo’s architecture has its own respective buffer holding only that pipeline's commands. The motivation is to enable per-pipeline monitoring, backpressure, and orderly context switching without cross-pipeline interference, as discussed by Yoo in Paragraph [0072].
Regarding Claim 53, it recites limitations similar in scope to the limitations of Claim 43 and therefore is rejected under the same rationale.
Claim(s) 48, 58 is/are rejected under 35 U.S.C. 103 as being unpatentable over Johnson (US 20180089881 A1), in view of McCrary et al. (US 20020023118 A1. Hereinafter McCrary) as applied to Claim 41, 51 above respectively and further in view of Jiao et al. (US 20080074433 A1, hereinafter Jiao).
Regarding Claim 48, the combination of Johnson and McCrary teaches the invention in Claim 41.
The combination further teaches further comprising: a scheduler [[configured to instantiate an emulation of at least one of the plurality of fixed-function hardware units on at least one of the plurality of programmable processing cores]] (Johnson, Paragraph [0136], "the GPU scheduler 1520 <read on scheduler> may generate a FIFO of work items 1622-1623 for each GPU 1530-1531, respectively").
But Johnson does not explicitly disclose that the scheduler instantiates an emulation of at least one of the plurality of fixed-function hardware units on at least one of the plurality of programmable processing cores.
However, Jiao teaches a scheduler configured to instantiate an emulation of at least one of the plurality of fixed-function hardware units on at least one of the plurality of programmable processing cores: (Jiao, Paragraph [0030], "Thread scheduler 210 may determine which hardware unit to use for each instruction, as described below. Thread scheduler 210 may then issue different instructions to different hardware units for execution in parallel"; [0024], "Elementary function core <read on fixed-function hardware unit> 230 may improve shader performance by computing the elementary functions in much less time than the time required to perform polynomial approximations of the elementary functions using simple instructions"; [0040], "Central thread scheduler 310 may implement an arbitration scheme and select one thread[i] for ALU core 220, one thread[j] for elementary function core 230 ... if these threads match the hardware units
Jiao and Johnson are analogous since both concern schedulers dispatching operations across programmable and fixed-function-type graphics hardware. Johnson provided a way of virtualizing GPU resources without specifying how the scheduler routes fixed-function operations to programmable units. Jiao provided a way of having the thread scheduler dispatch an elementary-function operation to either the dedicated fixed-function core or, alternatively, to the programmable ALU core using polynomial-approximation instructions — i.e., scheduler-instantiated software emulation of the fixed-function unit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Jiao's scheduler-controlled hardware-unit selection into the modified invention of Johnson, such that Johnson's GPU scheduler 1520 instantiates an emulation of a fixed-function unit on a programmable execution unit rather than routing to the dedicated unit. The motivation is to improve resource utilization and avoid idling on a single fixed-function unit when a programmable core is available, as discussed by Jiao in Paragraph [0029].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150221059 A1 METHOD AND SYSTEM OF A COMMAND BUFFER BETWEEN A CPU AND GPU
US 20150128136 A1 GRAPHICS PROCESSING UNIT CONTROLLER, HOST SYSTEM, AND METHODS
US 20110050713 A1 Hardware-Based Scheduling of GPU Work
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUJANG TSWEI whose telephone number is (571)272-6669. The examiner can normally be reached 8:30am-5:30pm EST.
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/YuJang Tswei/Primary Examiner, Art Unit 2614
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