Prosecution Insights
Last updated: May 29, 2026
Application No. 19/062,792

APPARATUS FOR SUPPLYING EMERGENCY POWER

Non-Final OA §103
Filed
Feb 25, 2025
Priority
Feb 13, 2020 — RE 10-2020-0017877 +2 more
Examiner
CHOWDHURI, SWARNA N
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Energy Solution, Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 10m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
262 granted / 344 resolved
+8.2% vs TC avg
Strong +22% interview lift
Without
With
+21.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
16 currently pending
Career history
376
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.6%
+46.6% vs TC avg
§102
11.6%
-28.4% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 344 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 16-20, 26, 33, 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0233785 (Na) in view of US 2020/0379050 (Imanaka). Regarding claim 16, Na teaches an apparatus (Fig. 1 shows a battery protection circuit module) comprising: a protection circuit (Fig. 1 shows a battery protection circuit module) configured to be connected to a battery (Fig. 1 shows battery Bc) and limit an available voltage range of the battery (Fig. 1 shows battery Bc) to a predetermined voltage range from a lower limit greater than 0 to an upper limit (battery Bc outputs a voltage range being greater than 0 to an upper limit) [0043-0045, 0057-0062]; a bypass circuit (Fig. 1 shows single field-effect transistor 112) connected in parallel to the protection circuit (Fig. 1 shows P-IC 118 i.e. protection circuit in parallel to single field-effect transistor 112 i.e. bypass circuit) and configured to form a bypass path from the battery (Fig. 1-3 shows single field-effect transistor 112 forming a bypass path) [0041] to bypass the protection circuit according to an operation state of the bypass circuit, the operation state of the bypass circuit including an on state and an off state (operation state of single field-effect transistor 112 to be ON/OFF forms bypass path for current output of battery Bc bypassing the P-IC 118 i.e. protection circuit) [0048, 0060]; and control the operation state of the bypass circuit to the on state or the off state based on whether a voltage of the battery is within a preset low-voltage range (P-IC 118 controls single field-effect transistor 112 1.e. bypass circuit by controlling the switching element to a turn-on state; single field-effect transistor 112 is turned on when the battery voltage range is normal (not over discharging) i.e. preset low-voltage range) [0057-62], the preset low-voltage range being within the predetermined voltage range and being closer to the lower limit than to the upper limit of the predetermined voltage range (preset low-voltage range of the battery Bc being within the predetermined voltage range and being closer to the lower limit and to the upper limit avoiding over discharge) [0046, 0048, 0062-0065]. However, Na does not teach control circuit. However, Imanaka teaches control circuit (Fig. 4 shows CPU 101 i.e. control circuit controlling switches 40 and 71) [0046-0047]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have control circuit as taught by Imanaka in order to have a separate CPU in order to ensure that the control circuit is not damaged. Regarding claim 17, Na teaches wherein when the bypass circuit is in the on state, the lower limit of the predetermined voltage range is released (single field-effect transistor 112 is turned on to release at least one of the lower limit and the upper limit on the available voltage range) [0062]. Regarding claim 18, Na teaches wherein to control the operation state of the bypass circuit to the on-state responsive to receiving an emergency power supply request (single field-effect transistor 112 is turned on to release at least one of the lower limit and the upper limit on the available voltage range to receiving a discharge request for battery Bc to supply emergency power supply) [0062-64]. However, Na does not teach control circuit. However, Imanaka teaches control circuit (Fig. 4 shows CPU 101 i.e. control circuit controlling switches 40 and 71) [0046-0047]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have control circuit as taught by Imanaka in order to have a separate CPU in order to ensure that the control circuit is not damaged. Regarding claim 19, Na teaches control the operation state of the bypass circuit to the on state during a preset initial run time when the battery starts operating (during normal charging i.e. preset initial run time single field-effect transistor 112 is turned on) [0060] However, Na does not teach control circuit. However, Imanaka teaches control circuit (Fig. 4 shows CPU 101 i.e. control circuit controlling switches 40 and 71) [0046-0047]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have control circuit as taught by Imanaka in order to have a separate CPU in order to ensure that the control circuit is not damaged. Regarding claim 20, Na teaches wherein: control the operation state of the bypass circuit to the on state responsive to determining that at least one of i) a discharge time during which the battery is continuously discharged with the voltage of the battery within the preset low-voltage range (discharge time during which the battery Bc is continuously discharged with the voltage of the battery within preset low-voltage range)[0063-64] and ii) the voltage of the battery when charging of the battery starts satisfies a predetermined condition. However, Na does not teach control circuit. However, Imanaka teaches control circuit (Fig. 4 shows CPU 101 i.e. control circuit controlling switches 40 and 71) [0046-0047]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have control circuit as taught by Imanaka in order to have a separate CPU in order to ensure that the control circuit is not damaged. Regarding claim 26, Na teaches wherein the preset low-voltage range is from the lower limit of the predetermined voltage range to a predetermined voltage lower than the upper limit of the predetermined voltage range (battery Bc outputs in preset low-voltage range being from the lower limit of the predetermined voltage range to a predetermined voltage lower than the upper limit of the predetermined voltage range during normal discharge any output beyond is considered over discharging which is to be prevented) [0070-0071]. Regarding claim 33, Na teaches a battery management system (BMS), comprising the apparatus according to claim 16 (detecting over discharge, overcharge and/or overcurrent of battery Bc is done as part of battery management system) [0041]. Regarding claim 35, Na teaches a battery pack, comprising the apparatus according to claim 16 (Fig. 1 shows battery Bc). Allowable Subject Matter Claims 21-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 27-32, 34 are allowed. REASONS FOR ALLOWANCE The following is an examiner’s statement of reasons for allowance: Regarding claim 27, the prior art does not teach: a first protection circuit configured to be connected to a battery and limit an available voltage range of the battery to a first predetermined voltage range from a first lower limit greater than 0 to a first upper limit; a second protection circuit configured to be connected to the battery and limit the available voltage range of the battery to a second predetermined voltage range from a second lower limit greater than 0 to a second upper limit, the second predetermined voltage range being different from the first predetermined voltage range; a first bypass circuit connected in parallel to the first protection circuit and configured to form a first bypass path from the battery to bypass the first protection circuit according to an operation state of the first bypass circuit, the operation state of the first bypass circuit including a first on state and a first off state; and a control circuit configured to control the operation state of the first bypass circuit to the first on state or the first off state based on whether a voltage of the battery is within a first preset low-voltage range, the preset low-voltage range being within the first predetermined voltage range and being closer to the first lower limit than to the first upper limit of the first predetermined voltage range. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SWARNA N CHOWDHURI whose telephone number is (571)431-0696. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at 571-272-7496. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SWARNA N. CHOWDHURI Examiner Art Unit 2836 /S.N.C/Examiner, Art Unit 2836 /REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Feb 25, 2025
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+21.5%)
3y 1m (~1y 10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 344 resolved cases by this examiner. Grant probability derived from career allowance rate.

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