Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 02/25/2025. These drawings are reviewed and accepted by examiners.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 11/06/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 02/25/2025. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 5 and 6 are rejected under 35 U.S.C. 102(a)(1)) as being anticipated by Lin et al. (Pub. No.: US 2021/0035621 A1; “Lin et al”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation, and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Lin et al in Figures 1-5 are directly disclosed a memory cell (a memory device 100 includes a memory array 200 includes a plurality of memory cells 210-1…210-4, Figures 1-2, paragraph 0025) comprising:
a memory element (a memory cells 210-1…210-4, Fig. 2A-2B); and
an ovonic threshold switch (OTS) (a resistance device 240 is an Ovonic Threshold Switch (OTS), paragraph 0030) selector electrically connected to the memory element (the memory cell 210) in series, the OTS selector (for example, a memory cells 210-1 includes OTS 230 and MTJ 230 are connected in series, Fig. 2A, paragraph 0030-0031) comprising:
a first electrode (a metal M3, Fig. 2B) having a first electrical conductivity.
a second electrode (a metal M2, Fig. 2B) having a second electrical conductivity which is higher than the first electrical conductivity; and
an OTS material portion (the resistance device 240) located between and directly contacting the first electrode (the metal M3) and the second electrode (the metal M2)(the resistance device 240 of OTS located between in contact with the metal M3 and the metal M2, Fig. 2B, see at least in Figures 1-4, paragraph 0016 to paragraph 0088S and the related disclosures).
Regarding dependent claim 5, Lin et al in Figures 1-5 are directly disclosed a memory cell (a memory device 100 includes a memory array 200 includes a plurality of memory cells 210-1…210-4, Figures 1-2, paragraph 0025) wherein the OTS (the resistance device of OTS 240) material portion comprises an amorphous chalcogenide material (the resistance device of OTS includes at least one of the elements in a chalcogenide group, paragraph 0036).
Regarding dependent claim 6, Lin et al in Figures 1-5 are directly disclosed a memory cell (a memory device 100 includes a memory array 200 includes a plurality of memory cells 210-1…210-4, Figures 1-2, paragraph 0025) wherein the memory element (a memory cell 210) comprises a magnetic tunnel junction (MTJ) (a memory cell 210 includes a MTJ 230, paragraph 0029).
Allowable Subject Matter
5. Claims 2-4 and 7-20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected dependent claim 2, the prior art fails to techs or suggest the claimed limitations, namely, the first electrode comprises a carbon or carbon nitride material directly contacting the OTS material portion, and the second electrode comprises a metal, metal alloy or a conductive metal nitride material directly contacting the OTS material portion.
With respected dependent claims 3-4, the prior art fails to tech or suggest the claimed limitations, namely, wherein the second electrode comprises an outer portion and an insert having the second electrical conductivity which is located between the outer portion and the OTS material portion, and directly contacting the OTS material portion, wherein: the first electrode consists essentially of carbon or carbon nitride material having the first electrical conductivity and directly contacting the OTS material portion; the outer portion of the second electrode consists essentially of carbon or carbon nitride material; and the insert comprises a conductive metal nitride material.
With respected dependent claims 7-19, the prior art fails to tech or suggest the claimed limitations, namely, the memory cell comprises a vertical stack of the memory element and the OTS selector; the MTJ comprises a vertical stack of a ferromagnetic reference layer, a ferromagnetic free layer and a tunnel barrier layer located between the ferromagnetic reference layer and the ferromagnetic free layer; and the OTS selector comprises a vertical stack of the first electrode, the OTS material portion and the second electrode, wherein: the MTJ comprises a top pinned MTJ in which the ferromagnetic reference layer is located above the ferromagnetic free layer; and the second electrode of the OTS selector is located above the OTS material portion, and the first electrode is located below the OTS material portion, wherein memory element is located below the OTS selector, wherein memory element is located above the OTS selector.
With respected dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, first electrically conductive lines laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction; second electrically conductive lines vertically spaced from the first electrically conductive lines, laterally extending along the second horizontal direction, and laterally spaced apart from each other along the first horizontal direction; and a two-dimensional array of the memory cells of claim 1 located at cross points between the first electrically conductive lines and the second electrically conductive lines
Conclusion
Examiner's note: Examiner has cited columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested by the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Deweerd et al (US. 2012/0025164 A1) discloses variable resistance memory with a selected device.
Steward et al (US. 11,271,040 B1) discloses memory device containing selectors with current focusing layer and methods of making the same.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights