Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 02/25/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed, i.e. including a detection circuit that detects whether an on-period of a transistor is shorter than a first time period and a first time measurement circuit that measures a second time period shorter than a period corresponding to a highest audible frequency.
The disclosure is objected to because of the following informalities: Paragraph [0077] recites “the detection circuit 103 outputs a low signal Sd”. The embodiment of Fig. 6 and Fig. 7 employs the detection circuit 107, whereas the detection circuit 103 is an element of the power factor correction IC 29a of Fig. 2 and outputs the signal Sb. It appears that “the detection circuit 103” should read as “the detection circuit 107”. Paragraphs [0041]-[0044], [0053]-[0054], [0058], [0063], [0069], [0075], and [0077] refer to an “oscillation voltage Vramp”, whereas Figs. 2-7 label the corresponding node “Vr”. Correction of the drawings or the specification is required so that the descriptive matter of the specification corresponds to the reference characters of the drawings (37 CFR 1.84(p)(5)). Appropriate correction is required.
Claim Objections
Claims 1-3 are objected to because of the following informalities: Regarding claim 1, in line 4, “including” appears that it should read as “including:”, because a colon is required to introduce the list of elements of the power supply circuit recited thereafter.
Regarding claim 2, in line 2, “comprising” appears that it should read as “further comprising”, because a dependent claim that adds an element should recite “further comprising” to make clear that the added element is in addition to the elements recited in the parent claim.
Regarding claim 3, in line 10, “including” appears that it should read as “including:”, because a colon is required to introduce the list of elements of the switching control circuit recited thereafter, consistent with line 11 of claim 1;
in line 13, “value and” appears that it should read as “value, and”, because a comma is required to separate the two parallel infinitive phrases recited for the driver circuit, consistent with line 14 of claim 1;
in lines 17-18, “a first time period, and” appears that it should read as “a first time period; and”, because a semicolon is required to separate the recited elements of the switching control circuit, consistent with lines 18-19 of claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Patent Application Publication US 2011/0221402 A1, hereinafter “Park”) in view of Lee et al. (US Patent Application Publication US 2013/0128640 A1, hereinafter “Lee”), and further in view of Chang et al. (US Patent Application Publication US 2023/0308018 A1, hereinafter “Chang”).
Regarding claim 1, Park discloses (see Fig. 2 and Fig. 3) a switching control circuit (power factor correction controller 100) for a power supply circuit (power factor correction circuit 1) that generates an output voltage (output voltage Vout generated across the capacitor Cout; see [0043] of Park) at a target level from an alternating current (AC) voltage (input AC power), the power supply circuit including an inductor (inductor L1) configured to receive a rectified voltage (input voltage Vin) from a full-wave rectifier circuit (bridge diode 20 formed of four diodes 21 to 24) configured to rectify the AC voltage (the bridge diode 20 generates the input voltage Vin by wave-rectifying the input AC power; see [0039] of Park), a transistor (power switch M formed of an NMOSFET) configured to control an inductor current (inductor current IL) flowing through the inductor (switching operation of the power switch M controls the inductor current IL flowing in the inductor L1; see [0040] and [0042] of Park), the switching control circuit configured to switch the transistor (the power factor correction controller 100 turns the power switch M on and off by a gate control signal Vgs applied to the connection terminal 7; see [0042] and [0045] of Park), the switching control circuit comprising: a driver circuit (PWM controller 170 together with the gate driver 180 formed of the PMOSFET 181 and the NMOSFET 182; see [0078] and [0084] of Park) configured to turn on the transistor when the inductor current becomes smaller than a predetermined value (the zero current detecting unit 120 determines that the current does not flow to the inductor L1 when the zero current detection voltage Vzcd reaches the zero current reference voltage and generates the zero current detection signal ZCD for turning on the power switch M, the zero current detection signal ZCD being input to the OR gate 172 and a rising edge of the output signal of the OR gate 172 being input to the set terminal S of the SR latch 173; see [0047], [0058], and [0081] of Park), and turn off the transistor when a time period corresponding to the output voltage elapses (the error amplification signal generator 160 generates the error amplification signal VCON from the division voltage VD obtained by dividing the output voltage Vout by the division resistors R1 and R2, the comparator 142 of the duty determining unit 140 outputs the high-level OFF control signal FS when the sawtooth wave signal SW that increases with a constant slope for a turn-on period of the power switch M reaches the error amplification signal VCON, and the OFF control signal FS is input through the OR gate 171 to the reset terminal R of the SR latch 173; see [0046], [0072], [0073], [0075], and [0080] of Park).
Park does not disclose a detection circuit configured to detect whether an on-period of the transistor is shorter than a first time period; and a first time measurement circuit configured to measure a second time period upon detecting that the on-period is shorter than the first time period, wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period, irrespective of the inductor current.
However, Lee teaches (see Fig. 4, Fig. 5, Fig. 6, and Fig. 7) a detection circuit (on-time detector 100 including the inverter 101, the constant current source 102, the comparator 103, the switching transistor 104, and the capacitor C2; see [0089] of Lee) configured to detect whether an on-period of the transistor (the on-time of the power switch M, represented by the ramp voltage VRAMP generated by the on-time detector 100 during the on-time and applied to the inversion terminal of the comparator 103) is shorter than a first time period (the minimum on-time, represented by the threshold voltage Vth applied to the non-inversion terminal of the comparator 103; the on-time detector 100 detects a period during which the on-time is shorter than or equal to the minimum on-time and generates the high-level detection signal VDE while the ramp voltage VRAMP is lower than or equal to the threshold voltage Vth; see [0088], [0096], [0097], and [0163] of Lee); and a first time measurement circuit (oscillator 300 including the sawtooth wave generator 310 and the clock signal generator 320; see [0128] of Lee) configured to measure a second time period (the period of the clock signal CLK, defined by the time for charging the capacitor C3 to the highest reference VH of the sawtooth wave VSAW and the time for discharging the capacitor C3 to the lowest reference VL of the sawtooth wave VSAW; see [0150] and [0151] of Lee) upon detecting that the on-period is shorter than the first time period (the counter 210 of the frequency controller 200 receives the detection signal VDE and counts the period during which the on-time is shorter than or equal to the minimum on-time, the counter 210 generates the first decrease signal DS1 when the counted period reaches the threshold period, the first SR latch 220 generates the first frequency control signal FS1 according to the first decrease signal DS1, and the oscillator 300 controls the period of the clock signal CLK according to the first frequency control signal FS1; see [0100], [0102], [0103], [0110], and [0127] of Lee), wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period (when the decreasing sawtooth wave VSAW reaches the lowest reference VL, the clock signal generator 320 increases the clock signal CLK, the clock signal CLK is input to the set terminal S of the SR latch 510 so that the high-level gate control signal VC is generated, and the gate driver 400 generates the enable-level gate signal VG that turns on the power switch M; see [0083], [0084], [0152], [0154], and [0161] of Lee), irrespective of the inductor current (the power switch M is turned on by the clock signal CLK of the oscillator 300, whereas the drain current Ids flowing through the sense resistor RS is used only to turn off the power switch M through the switching comparator 530 and the reset terminal R of the SR latch 510; see [0071], [0078], [0081], and [0083] of Lee).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Park to include a detection circuit configured to detect whether an on-period of the transistor is shorter than a first time period, and a first time measurement circuit configured to measure a second time period upon detecting that the on-period is shorter than the first time period, wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period, irrespective of the inductor current, as taught by Lee, because it can help identify the reduced load condition of the power supply circuit directly from the on-period of the transistor, which shortens as the load decreases, and thereby govern the turn-on instant of the transistor by a measured time period rather than by the zero current point of the inductor current, so that the switching operation is maintained at a controlled period. Examiner’s Note: Park already provides the timer 174 within the PWM controller 170 that generates the ON time pulse signal fmin so as to turn on the power switch M by force at every predetermined maximum set period, and thereby controls the switching operation of the power switch M with the minimum switching frequency, when no zero current point of the inductor current IL is detected (see [0048], [0079], and [0081] of Park), so that supplying the on-period of the transistor as the condition governing such a timed turn-on uses an indicator of the load condition already recognized in the art.
Park in view of Lee does not disclose wherein the second time period is shorter than a period corresponding to a highest audible frequency.
However, Chang teaches (see Fig. 1) wherein the second time period is shorter than a period corresponding to a highest audible frequency (the timer 110 generates the input signal TS1 indicative of whether the predetermined amount of time TMAX has elapsed since activation of the drive signal GD1, the driver circuit 130 generates the drive signal GD1 that turns on the switch Q1 according to the input signal TS1 so that the drive signal GD1 has a period equal to the predetermined amount of time TMAX, and the predetermined amount of time TMAX is equal to a maximum permissible switching period of the switching regulator 100, a reciprocal of which is higher than an upper limit of the audible frequency range, the audible frequency range being from 20 Hz to 20 kHz; see [0002], [0020], [0021], [0025], [0026], and [0032] of Chang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the switching control circuit of Park as modified in view of Lee wherein the second time period is shorter than a period corresponding to a highest audible frequency, as taught by Chang, because it can help keep the switching frequency of the transistor higher than the upper limit of the audible frequency range as the load decreases and the on-period of the transistor shortens, and thereby reduce or eliminate the audible noise that is produced due to the piezoelectric effect in capacitors when the switching frequency falls within the audible frequency range (see [0002] and [0026] of Chang). Examiner’s Note: This benefit is of particular consequence in the switching control circuit of Park as modified in view of Lee, because the modification decreases the switching frequency in response to the detection that the on-time is shorter than or equal to the minimum on-time (see [0100] of Lee), which drives the switching frequency toward the audible frequency range that Chang bounds.
Regarding claim 3, Park discloses (see Fig. 2 and Fig. 3) a power supply circuit (power factor correction circuit 1) configured to generate an output voltage (output voltage Vout generated across the capacitor Cout; see [0043] of Park) at a target level from an alternating current (AC) voltage (input AC power), the power supply circuit comprising: an inductor (inductor L1) configured to receive a rectified voltage (input voltage Vin) from a full-wave rectifier circuit (bridge diode 20 formed of four diodes 21 to 24) configured to rectify the AC voltage (the bridge diode 20 generates the input voltage Vin by wave-rectifying the input AC power; see [0039] of Park); a transistor (power switch M formed of an NMOSFET) configured to control an inductor current (inductor current IL) flowing through the inductor (switching operation of the power switch M controls the inductor current IL flowing in the inductor L1; see [0040] and [0042] of Park); and a switching control circuit (power factor correction controller 100) configured to switch the transistor (the power factor correction controller 100 turns the power switch M on and off by a gate control signal Vgs applied to the connection terminal 7; see [0042] and [0045] of Park), the switching control circuit including a driver circuit (PWM controller 170 together with the gate driver 180 formed of the PMOSFET 181 and the NMOSFET 182; see [0078] and [0084] of Park) configured to turn on the transistor when the inductor current becomes smaller than a predetermined value (the zero current detecting unit 120 determines that the current does not flow to the inductor L1 when the zero current detection voltage Vzcd reaches the zero current reference voltage and generates the zero current detection signal ZCD for turning on the power switch M, the zero current detection signal ZCD being input to the OR gate 172 and a rising edge of the output signal of the OR gate 172 being input to the set terminal S of the SR latch 173; see [0047], [0058], and [0081] of Park) and turn off the transistor when a time period corresponding to the output voltage elapses (the error amplification signal generator 160 generates the error amplification signal VCON from the division voltage VD obtained by dividing the output voltage Vout by the division resistors R1 and R2, the comparator 142 of the duty determining unit 140 outputs the high-level OFF control signal FS when the sawtooth wave signal SW that increases with a constant slope for a turn-on period of the power switch M reaches the error amplification signal VCON, and the OFF control signal FS is input through the OR gate 171 to the reset terminal R of the SR latch 173; see [0046], [0072], [0073], [0075], and [0080] of Park).
Park does not disclose a detection circuit configured to detect whether an on-period of the transistor is shorter than a first time period, and a first time measurement circuit configured to measure a second time period upon detecting that the on-period is shorter than the first time period, wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period, irrespective of the inductor current.
However, Lee teaches (see Fig. 4, Fig. 5, Fig. 6, and Fig. 7) a detection circuit (on-time detector 100 including the inverter 101, the constant current source 102, the comparator 103, the switching transistor 104, and the capacitor C2; see [0089] of Lee) configured to detect whether an on-period of the transistor (the on-time of the power switch M, represented by the ramp voltage VRAMP generated by the on-time detector 100 during the on-time and applied to the inversion terminal of the comparator 103) is shorter than a first time period (the minimum on-time, represented by the threshold voltage Vth applied to the non-inversion terminal of the comparator 103; the on-time detector 100 detects a period during which the on-time is shorter than or equal to the minimum on-time and generates the high-level detection signal VDE while the ramp voltage VRAMP is lower than or equal to the threshold voltage Vth; see [0088], [0096], [0097], and [0163] of Lee), and a first time measurement circuit (oscillator 300 including the sawtooth wave generator 310 and the clock signal generator 320; see [0128] of Lee) configured to measure a second time period (the period of the clock signal CLK, defined by the time for charging the capacitor C3 to the highest reference VH of the sawtooth wave VSAW and the time for discharging the capacitor C3 to the lowest reference VL of the sawtooth wave VSAW; see [0150] and [0151] of Lee) upon detecting that the on-period is shorter than the first time period (the counter 210 of the frequency controller 200 receives the detection signal VDE and counts the period during which the on-time is shorter than or equal to the minimum on-time, the counter 210 generates the first decrease signal DS1 when the counted period reaches the threshold period, the first SR latch 220 generates the first frequency control signal FS1 according to the first decrease signal DS1, and the oscillator 300 controls the period of the clock signal CLK according to the first frequency control signal FS1; see [0100], [0102], [0103], [0110], and [0127] of Lee), wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period (when the decreasing sawtooth wave VSAW reaches the lowest reference VL, the clock signal generator 320 increases the clock signal CLK, the clock signal CLK is input to the set terminal S of the SR latch 510 so that the high-level gate control signal VC is generated, and the gate driver 400 generates the enable-level gate signal VG that turns on the power switch M; see [0083], [0084], [0152], [0154], and [0161] of Lee), irrespective of the inductor current (the power switch M is turned on by the clock signal CLK of the oscillator 300, whereas the drain current Ids flowing through the sense resistor RS is used only to turn off the power switch M through the switching comparator 530 and the reset terminal R of the SR latch 510; see [0071], [0078], [0081], and [0083] of Lee).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power supply circuit of Park to include a detection circuit configured to detect whether an on-period of the transistor is shorter than a first time period, and a first time measurement circuit configured to measure a second time period upon detecting that the on-period is shorter than the first time period, wherein upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period, irrespective of the inductor current, as taught by Lee, because it can help identify the reduced load condition of the power supply circuit directly from the on-period of the transistor, which shortens as the load decreases, and thereby govern the turn-on instant of the transistor by a measured time period rather than by the zero current point of the inductor current, so that the switching operation is maintained at a controlled period. Examiner’s Note: Park already provides the timer 174 within the PWM controller 170 that generates the ON time pulse signal fmin so as to turn on the power switch M by force at every predetermined maximum set period, and thereby controls the switching operation of the power switch M with the minimum switching frequency, when no zero current point of the inductor current IL is detected (see [0048], [0079], and [0081] of Park), so that supplying the on-period of the transistor as the condition governing such a timed turn-on uses an indicator of the load condition already recognized in the art.
Park in view of Lee does not disclose wherein the second time period is shorter than a period corresponding to a highest audible frequency.
However, Chang teaches (see Fig. 1) wherein the second time period is shorter than a period corresponding to a highest audible frequency (the timer 110 generates the input signal TS1 indicative of whether the predetermined amount of time TMAX has elapsed since activation of the drive signal GD1, the driver circuit 130 generates the drive signal GD1 that turns on the switch Q1 according to the input signal TS1 so that the drive signal GD1 has a period equal to the predetermined amount of time TMAX, and the predetermined amount of time TMAX is equal to a maximum permissible switching period of the switching regulator 100, a reciprocal of which is higher than an upper limit of the audible frequency range, the audible frequency range being from 20 Hz to 20 kHz; see [0002], [0020], [0021], [0025], [0026], and [0032] of Chang).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the power supply circuit of Park as modified in view of Lee wherein the second time period is shorter than a period corresponding to a highest audible frequency, as taught by Chang, because it can help keep the switching frequency of the transistor higher than the upper limit of the audible frequency range as the load decreases and the on-period of the transistor shortens, and thereby reduce or eliminate the audible noise that is produced due to the piezoelectric effect in capacitors when the switching frequency falls within the audible frequency range (see [0002] and [0026] of Chang). Examiner’s Note: This benefit is of particular consequence in the power supply circuit of Park as modified in view of Lee, because the modification decreases the switching frequency in response to the detection that the on-time is shorter than or equal to the minimum on-time (see [0100] of Lee), which drives the switching frequency toward the audible frequency range that Chang bounds.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “a second time measurement circuit configured to measure a third time period when the transistor is turned off, the third time period being shorter than the second time period, wherein when the on-period is longer than the first time period, the driver circuit turns on the transistor based on completion of measurement of the third time period”. The closest prior art, Park, discloses the timer 174 that generates the ON time pulse signal fmin so as to turn on the power switch M by force at every predetermined maximum set period when the power switch M is not turned on during that period (see [0079] of Park), but the maximum set period of Park is the only measured period disclosed and is not a further period that is shorter than a measured period and that governs the turning on of the power switch M when the on-period is longer than the first time period, and therefore Park fails to disclose or teach the above limitation. Chang discloses the timer 160 that measures the predetermined amount of time TEXT elapsed since the inductor current IL reached the current threshold after the switch Q1 is turned off, the timeout period of the timer 160 serving as a maximum permissible time interval between the time at which the switch Q2 is turned on and the time at which the switch Q2 is turned off and therefore falling within the predetermined amount of time TMAX (see [0030] and [0056] of Chang, and see Fig. 5B of Chang), but the driver circuit 130 of Chang turns off the switch Q2 in response to the input signal TS2 at the completion of the predetermined amount of time TEXT rather than turning on a transistor, and the predetermined amount of time TEXT is measured while the mode is enabled rather than when the on-period is longer than the first time period, and therefore Chang also fails to disclose or teach the above limitation. Lee discloses the delay unit 230 that maintains the second SR latch 240 in the reset state for a delay period after the frequency decrease of the clock signal (see [0112] of Lee), but the delay period of Lee blocks a further decrease of the frequency of the clock signal rather than governing the turning on of the power switch M, and therefore Lee also fails to disclose or teach the above limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2012/0223691 A1 discloses a power factor correction controller that enters an ultrasonic mode in which the switching frequency is maintained above the audible frequency band when the on-time of the power switch has reached its minimum value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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