Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-9 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20230023618 A1) in view of Jeon et al. (US 20160018454 A1).
Regarding claims 1, 8, and 9: Zhang discloses an apparatus and techniques for detecting and isolating defective blocks of memory cells in a multi-plane operation via word line leakage detection comprising: A semiconductor storage device (100, FIG. 1A) comprising: a first plane and a second plane (planes e.g., P0 and P1, par. 107, FIG. 3A), each including a plurality of blocks (blocks BLK within planes, par. 107, FIG. 3A), each of which is a set of a plurality of memory cell transistors (memory cells 390a-d within blocks, par. 126, FIG. 3C); a memory controller configured to control the semiconductor storage device (memory controller 122, FIG. 1A), a signal line (from path 320, FIG. 3A) configured to apply voltages (from word line Wln voltage driver 115, FIG. 3A) to a first word line (through 320a, FIG> 3A) connected to a gate of a first memory cell transistor (WL connected to gate of transistor of a memory cell, FIG. 3A and 7A) contained in a first block of the first plane (FIG. 7A uses BLK0-0 of Plane P0) and a second word line (through 320b, FIG. 3A) connected to a gate of a second memory cell transistor contained in a second block of the second plane (FIG. 3A and 7A can be applied to other blocks of other planes, such as memory cells in BLK1-0 of plane P1); a control unit (power control circuit 115, FIG. 1A) configured to control the first plane and the second plane (power control circuit includes voltage drivers to the blocks of the planes, par. 109, FIG. 3A), wherein when determination results produced by the determination circuit indicate that there is leakage in the first word line and that there is no leakage in the second word line (determining word line leakage within multi-plane operation of FIG. 15, par. 194-196), the control unit registers the first block as a bad block (defective faulty block, par. 51, 177, and 196) and registers the second block as a victim block able to be used as a good block (good, non-defective, non-faulty blocks to continue to be programmed without being affected by neighboring disturbs, par. 51, 177, and 196).
Zhang does not disclose a determination circuit configured to determine based on the voltage of the signal line whether there is any leakage in the first word line or the second word line.
Jeon does disclose a leakage current detection device (10, FIG. 2) configured to determine based on the voltage of the signal line whether there is any leakage in the first word line or the second word line (detect voltage of driven word lines to detect leakage, par. 80-81).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Zhang with the detection circuit of Jeon to allow the system to have a dedicated detection circuit to aid in determining word line leakage like the claimed invention.
Claim(s) 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20230023618 A1) in view of Jeon et al. (US 20160018454 A1), in further view of Kuramori (US 20040178844 A1).
Regarding claim 2: Zhang discloses an apparatus and techniques for detecting and isolating defective blocks of memory cells in a multi-plane operation via word line leakage detection, further comprising: a first switching element (row decoder/word line switches 315/316) can be a switch provided between the signal line and the first plane (between lines 320 and blocks of the plane P0, FIG. 3A-3B); a second switching element (row decoder/word line switches 315/316) provided between the signal line and the second plane (between lines 320 and blocks of the plane P1, FIG. 3A-3B).
Zhang does not disclose the determination circuit: applies a predetermined voltage to the signal line from the voltage generation circuit, then turns on the first switching element, thereby connecting the signal line to the first word line, turns off the second switching element and the third switching element, thereby placing the signal line in an electrically floating state, and determines based on a resulting first voltage of the signal line whether there is any leakage in the first word line, and applies the predetermined voltage to the signal line from the voltage generation circuit, then turns on the second switching element, thereby connecting the signal line to the gate of the second memory cell transistor, turns off the first switching element and the third switching element, thereby placing the signal line in an electrically floating state, and determines based on a resulting second voltage of the signal line whether there is any leakage in the second word line.
Jeon does disclose a leakage current detection device (10, FIG. 2), wherein the determination circuit: applies a predetermined voltage to the signal line from the voltage generation circuit (drive voltage VD to test line TEST_LN, FIG. 18; step S200 of FIG. 19), then turns on the first switching element (through address decoder 601, FIG. 18), thereby connecting the signal line to the first word line (test line TEST_LN may also correspond to a word line of the memory cell array, par. 68), turns off the second switching element and the third switching element (such as switch 120 turned off, par. 87), thereby placing the signal line in an electrically floating state (floating test line TEST_LN, step S400 of FIG. 19), and determines based on a resulting first voltage of the signal line whether there is any leakage in the first word line (determines leakage detection by comparing test voltage VD to a reference, S500 of FIG. 19), and applies the predetermined voltage to the signal line from the voltage generation circuit, then turns on the second switching element, thereby connecting the signal line to the gate of the second memory cell transistor, turns off the first switching element and the third switching element, thereby placing the signal line in an electrically floating state, and determines based on a resulting second voltage of the signal line whether there is any leakage in the second word line (same operation as above shown in FIG. 19 can be applied to another selected word line, par. 69-70).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Zhang with the detection circuit of Jeon to allow the system to have a dedicated detection circuit to aid in determining word line leakage like the claimed invention.
Zhang and Jeon do not disclose a voltage generation circuit configured to apply a voltage to the signal line; and a third switching element provided between the signal line and the voltage generation circuit.
Kuramori does disclose an internal power supply circuit (FIG. 1) detailing: a voltage generation circuit (voltage generators 20, FIG. 1) configured to apply a voltage to the signal line (output unit 40 as VDD, FIG. 1); and a third switching element (voltage switch 30, FIG. 1) provided between the signal line (out of output unit 40 as VDD, FIG. 1) and the voltage generation circuit (e.g., 20a, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Zhang and Jeon with the voltage supply generator configuration of Kuramori to have the same internal configuration as the claimed invention.
Regarding claim 3: Zhang does not disclose the determination circuit includes a comparison circuit configured to compare the voltage of the signal line with a predetermined reference voltage and output a signal indicating comparison results; and the comparison circuit compares the first voltage of the signal line with the reference voltage and thereby outputs a signal indicating whether there is any leakage in the first word line, and compares the second voltage of the signal line with the reference voltage and thereby outputs a signal indicating whether there is any leakage in the second word line.
Jeon does disclose a leakage current detection device (10, FIG. 2), wherein: the determination circuit (leakage current detection device 10, FIG. 1) includes a comparison circuit (comparator 300, FIG. 1) configured to compare the voltage of the signal line (connected TEST_LN, FIG. 1) with a predetermined reference voltage (reference voltage VREF2, FIG. 1) and output a signal indicating comparison results (test result signal TEST_RE, FIG. 1); and the comparison circuit compares the first voltage of the signal line with the reference voltage (compares driven TEST_LN to VREF2, par. 79-81, FIG. 1) and thereby outputs a signal indicating whether there is any leakage in the first word line (test result signal TEST_RE may indicate whether a leakage current flows from the test line TEST_LN, par. 81), and compares the second voltage of the signal line with the reference voltage and thereby outputs a signal indicating whether there is any leakage in the second word line (same operation as above can be applied to another selected word line, par. 69-70).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Zhang and Kuramori with the detection device of Jeon to allow the system to compare and determine possible word line leakage like the claimed invention.
Regarding claim 4: Zhang does not disclose wherein the reference voltage is equal to or lower than the predetermined voltage.
Jeon does disclose a leakage current detection device (10, FIG. 2), wherein: wherein the reference voltage is equal to or lower than the predetermined voltage (driven voltage at TEST_LN is stored in a capacitor C1 coupled to the detection node D_ND, the comparator detects the floated D_ND which may become lower than the reference VREF2 in the case of leakage current, thus the predetermined voltage is equal or higher than the reference voltage, par. 81).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Zhang and Kuramori with the configuration of Jeon to allow the detection circuit to have the same relationship between the drive voltage and the reference voltage for comparison as the claimed invention.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20230023618 A1) in view of Jeon et al. (US 20160018454 A1), in further view of Li et al. (US 20120008384 A1).
Regarding claim 7: Zhang does not disclose the control unit performs write operations into the first memory cell transistor and the second memory cell transistor, and then performs a determination process using the determination circuit to check whether there is any leakage in the first word line or the second word line.
Li does disclose techniques and corresponding circuitry are presented for the detection of word line leakage in a memory array wherein the control unit performs write operations (program-verify operations of cells, par. 13) into the first memory cell transistor and the second memory cell transistor (cells of memory array 200, par. 13, FIG. 4), and then performs a determination process using the determination circuit to check whether there is any leakage (failures after stress of multiple program cycles, word lines can be checked after programming, par. 81) in the first word line or the second word line.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Zhang and Jeon with the operation of Li to allow the system to determine leakages and other issues post write operation as the memory cells of the array continue to degrade over time, to ensure more efficient operation during use.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having a fourth switching element provided between the comparison circuit and the signal line as in claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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