Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is rejected under 35 U.S.C. 103 as being unpatentable over Horiguchi et al. (US 20080290932 A1) in view of Lam et al. (US 20050264271 A1).
Regarding claim 1: Horiguchi discloses a semiconductor integrated circuit device (FIG. 1), comprising: a plurality of step-down circuits (plurality of step-down power supply circuits20-21 and 30-32, par. 35, FIG. 1) configured to step down a first voltage that is input (VREFA, FIG. 1) and to output a first stepped-down voltage (output terminal VDDA, FIG. 1) or to step down a second voltage that is input (VREFD, FIG. 1) and to output a second stepped-down voltage (output terminal VDDD, FIG. 1).
Horiguchi does not disclose a plurality of input switches connected to input terminals of the plurality of step-down circuits, respectively, each of the input switches being configured to switch an input to the corresponding input terminal to either the first voltage or the second voltage; and a plurality of output switches connected to output terminals of the plurality of step-down circuits, respectively, each of the output switches being configured to switch an output from the corresponding output terminal to either a first output node or a second output node.
Lam does disclose a multiple input multiple output buck switching converter (FIG. 7) comprising: a plurality of input switches (input switches SA, FIG. 7) connected to input terminals of the plurality of step-down circuits (switching converter able to implement step-down, par. 5) respectively, each of the input switches being configured to switch an input to the corresponding input terminal to either the first voltage or the second voltage (switches between input voltage of I/O1 and I/O2, FIG. 7); and a plurality of output switches (output switches SB, FIG. 7) connected to output terminals of the plurality of step-down circuits, respectively, each of the output switches being configured to switch an output from the corresponding output terminal to either a first output node or a second output node (switches between outputs I/O3 and I/O4, FIG. 7).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the step down circuits of Horiguchi with the switches configuration of Lam to allow the step down circuits to easily switch between different sets of input reference voltages like the claimed invention.
Claim(s) 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Horiguchi et al. (US 20080290932 A1) in view of Lam et al. (US 20050264271 A1), in further view of Xu et al. (US 20020118000 A1).
Regarding claim 2: Horiguchi discloses a semiconductor integrated circuit device (FIG. 1), comprising: the plurality of step-down circuits include first, second, third, and fourth step-down circuits (plurality of step-down power supply circuits20-21 and 30-32, par. 35, FIG. 1).
Horiguchi does not disclose the semiconductor integrated circuit, wherein the plurality of input switches includes first, second, third, and fourth input switches, the plurality of output switches includes first, second, third, and fourth output switches.
Lam does disclose a multiple input multiple output buck switching converter (FIG. 7) comprising: the plurality of input switches includes first, second, third, and fourth input switches (plurality of input switches Si1-Sim, FIG. 1), the plurality of output switches includes first, second, third, and fourth output switches (plurality of output switches So1-Son, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the step down circuits of Horiguchi with the configuration of Lam to allow the circuits to have multiple switches to allow different reference voltages to be stepped down like the claimed invention.
Horiguchi and Lam do not disclose the plurality of input switches includes first, second, third, and fourth input switches, the plurality of output switches includes first, second, third, and fourth output switches, the first input switch, the second input switch, the first output switch, and the second output switch are operated in synchronization with each other, and the third input switch, the fourth input switch, the third output switch, and the fourth output switch operate in synchronization with each other and complementary to the first input switch, the second input switch, the first output switch, and the second output switch.
Xu does disclose a multiphase coupled buck converter comprising: the first input switch, the second input switch, the first output switch, and the second output switch are operated in synchronization with each other (plurality of switches in FIG. 1 where the two step down buck converters are in sync with each other, par. 8, FIG. 1), and the third input switch, the fourth input switch, the third output switch, and the fourth output switch operate in synchronization with each other and complementary (plurality of switches in the two step down buck converters of FIG. 39 are controlled in complementary fashion for different phases, par. 127, FIG. 39) to the first input switch, the second input switch, the first output switch, and the second output switch.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Horiguchi and Lam with the configuration of Xu to allow the switches of the step down circuits to be adjusted to be in sync and complementary as in the claimed invention.
Regarding claim 9: Horiguchi discloses a semiconductor integrated circuit device (FIG. 1), comprising: a step-down circuit (e.g. step-down power supply circuit 20, FIG. 20) configured to step down a first voltage (VREFA, FIG. 1) that is input and to output a first stepped-down voltage (output terminal VDDA, FIG. 1) or to step down a second voltage (VREFD, FIG. 1) that is input and to output a second stepped-down voltage (output terminal VDDD, FIG. 1), and a control circuit (analog circuit 40/digital circuit 50, FIG. 1) configured to control reading and writing of a semiconductor memory device (program execution state, FIG. 18) using the voltage at the first output node and the second output node (VDDA/VDDD, FIG. 7).
Horiguchi does not disclose an input switch connected to an input terminal of the step-down circuit, the input switch being configured to switch an input to the input terminal to either the first voltage or the second voltage, and an output switch connected to an output terminal of the step-down circuit, the output switch being configured to switch an output from the output terminal to either a first output node or a second output node, and a signal generator circuit configured to generate and output control signals for controlling the input switch and the output switch.
Lam does disclose a multiple input multiple output buck switching converter (FIG. 7) comprising: an input switch (input switch SA, FIG. 7) connected to an input terminal of the step-down circuit (switching converter 70, FIG. 7), the input switch being configured to switch an input to the input terminal to either the first voltage or the second voltage (Between input voltage of I/O1 and I/O2, FIG. 7), and an output switch (output switch SB, FIG. 7) connected to an output terminal of the step-down circuit, the output switch being configured to switch an output from the output terminal to either a first output node or a second output node (Between outputs I/O3 and I/O4, FIG. 7), and a signal generator circuit configured to generate and output control signals for controlling the input switch and the output switch (switch on and off operations controlled by a feedback controller 21, par. 19).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the step down circuits of Horiguchi with the configuration of Lam to allow the circuit to have the input and output switches operations to allow different reference voltages to be stepped down like the claimed invention.
Regarding claim 16: Horiguchi discloses a semiconductor integrated circuit device (FIG. 1), comprising: a plurality of step-down circuits (plurality of step-down power supply circuits20-21 and 30-32, par. 35, FIG. 1) configured to step down a first voltage that is input (VREFA, FIG. 1) and to output a first stepped-down voltage (output terminal VDDA, FIG. 1) or to step down a second voltage that is input (VREFD, FIG. 1) and to output a second stepped-down voltage (output terminal VDDD, FIG. 1), and a plurality of step-down circuits include first, second, third, and fourth step-down circuits (plurality of step-down power supply circuits20-21 and 30-32, par. 35, FIG. 1).
Horiguchi does not disclose a plurality of input switches connected to input terminals of the plurality of step-down circuits, respectively, each of the input switches being configured to switch an input to the corresponding input terminal to either the first voltage or the second voltage; and a plurality of output switches connected to output terminals of the plurality of step-down circuits, respectively, each of the output switches being configured to switch an output from the corresponding output terminal to either a first output node or a second output node, and the plurality of input switches includes first, second, third, and fourth input switches; the plurality of output switches includes first, second, third, and fourth output switches.
Lam does disclose a multiple input multiple output buck switching converter (FIG. 7) comprising: a plurality of input switches (input switches SA, FIG. 7) connected to input terminals of the plurality of step-down circuits (switching converter able to implement step-down, par. 5) respectively, each of the input switches being configured to switch an input to the corresponding input terminal to either the first voltage or the second voltage (switches between input voltage of I/O1 and I/O2, FIG. 7); and a plurality of output switches (output switches SB, FIG. 7) connected to output terminals of the plurality of step-down circuits, respectively, each of the output switches being configured to switch an output from the corresponding output terminal to either a first output node or a second output node (switches between outputs I/O3 and I/O4, FIG. 7), and the plurality of input switches includes first, second, third, and fourth input switches (plurality of input switches Si1-Sim, FIG. 1), the plurality of output switches includes first, second, third, and fourth output switches (plurality of output switches So1-Son, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the step down circuits of Horiguchi with the switches configuration of Lam to allow the step down circuits to easily switch between different sets of input reference voltages like the claimed invention.
Horiguchi and Lam do not disclose a control method comprising: operating the first input switch, the second input switch, the first output switch, and the second output switch in synchronization with each other, and operating the third input switch, the fourth input switch, the third output switch, and the fourth output switch in synchronization with each other and complementary to the first input switch, the second input switch, the first output switch, and the second output switch.
Xu does disclose a multiphase coupled buck converter comprising: the first input switch, the second input switch, the first output switch, and the second output switch are operated in synchronization with each other (plurality of switches in FIG. 1 where the two step down buck converters are in sync with each other, par. 8, FIG. 1), and the third input switch, the fourth input switch, the third output switch, and the fourth output switch operate in synchronization with each other and complementary (plurality of switches in the two step down buck converters of FIG. 39 are controlled in complementary fashion for different phases, par. 127, FIG. 39) to the first input switch, the second input switch, the first output switch, and the second output switch.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Horiguchi and Lam with the configuration of Xu to allow the switches of the step down circuits to be adjusted to be in sync and complementary as in the claimed invention.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Horiguchi et al. (US 20080290932 A1) in view of Lam et al. (US 20050264271 A1), in further view of Mallinson (US 4608529 A).
Regarding claim 8: Horiguchi does not disclose the first voltage is a voltage that is applied to a first diode having one end connected to a first constant current source, and the second voltage is a voltage that is applied to a second diode that is connected in parallel to the first diode and has one end connected to a second constant current source.
Mallinson does disclose a constant voltage circuit wherein the first voltage is a voltage that is applied to a first diode (Z1, FIG. 3) having one end connected to a first constant current source (14, FIG. 3), and the second voltage is a voltage that is applied to a second diode (Z2, FIG. 3) that is connected in parallel to the first diode (parallel to Z1, FIG. 3) and has one end connected to a second constant current source (30, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Horiguchi and Lam with the configuration of Mallinson to allow the reference voltage generated to pass through the diodes before being output like the claimed invention.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Horiguchi et al. (US 20080290932 A1) in view of Lam et al. (US 20050264271 A1), in further view of Xu et al. (US 20020118000 A1), in further view of Mallinson (US 4608529 A).
Regarding claim 14: Horiguchi does not disclose the first voltage is a voltage that is applied to a first diode having one end connected to a first constant current source, and the second voltage is a voltage that is applied to a second diode that is connected in parallel to the first diode and has one end connected to a second constant current source.
Mallinson does disclose a constant voltage circuit wherein the first voltage is a voltage that is applied to a first diode (Z1, FIG. 3) having one end connected to a first constant current source (14, FIG. 3), and the second voltage is a voltage that is applied to a second diode (Z2, FIG. 3) that is connected in parallel to the first diode (parallel to Z1, FIG. 3) and has one end connected to a second constant current source (30, FIG. 3).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Horiguchi, Lam, and Xu with the configuration of Mallinson to allow the reference voltage generated to pass through the diodes before being output like the claimed invention.
Allowable Subject Matter
Claims 3-7, 10-13, 15, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: the structure of each of the first, second, third, and fourth step-down circuits includes a first switch configured to control charging of an input voltage that is input through the input terminal, a first capacitor charged with the input voltage, a second capacitor that is stepped down in voltage by being connected to the charged first capacitor in parallel, a second switch configured to connect the first capacitor and the second capacitor to each other and to control a step-down operation of the input voltage, a third switch configured to discharge charge in the second capacitor, and a fourth switch configured to cut-off the output terminal when the second capacitor is discharged or the step-down operation is executed as in claims 3, 10, and 17; and a current generating circuit connected to the first output node and the second output node and configured to generate an output current that is supplied to the control circuit as in claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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