Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 1-20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. [0095] of the instant application recites the following:
Optionally, referring to FIG. 4, in the embodiments of the present disclosure, the orthographic projection of the first light-shielding layer 10 on the base substrate 00 covers the orthographic projection of the active layer 40 on the base substrate 00. In this way, a better light-shielding effect can be further ensured.
However, figure 4 and [0095] of the specification fails to enable a skilled artisan how to make and/or use “an orthographic projection of the active layer on the base substrate falls within an orthographic projection of the first light-shielding layer on the base substrate.” (emphasis added) as set forth in the penultimate line through ultimate line of claim 1. Similar lack of enablement exists in claims 12 and 15.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, in the penultimate line through the ultimate line of claim 1 “an orthographic projection of the active layer on the base substrate falls within an orthographic projection of the first light-shielding layer on the base substrate” is set forth. However, it is unclear as to what the metes and bounds are of the claim language “falls within” with respect to the “active layer” and the “first light-shielding layer”. Similar indefiniteness exists in claims 12 and 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, 12-13 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al (US 2020/0044092).
As per claim 1 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: A gate driving circuit, comprising:
a plurality of first transistors 110/160; wherein at least one first target transistor 160 of the plurality of first transistors 110/160 comprises:
a first light-shielding layer 170 disposed on a side of a base substrate 101, the first light-shielding layer 170 being made of a conductive material {[0059] For example, a metal or metal oxide material or the like may be used to prepare the second light shielding layer 170. }; and
a first gate metal layer 162 { [0053] The second gate electrode 162 may be made of metal, transparent conductive material, or other suitable materials.} and a first source/drain metal layer 163/164 { [0055] The second source electrode 163 and the second drain electrode 164 are disposed on the second insulating layer 133 and are electrically connected to the second active layer 161, respectively (for example, the second source electrode 163 and the second drain electrode 164 are disposed directly on two ends of the second active layer 161 and overlap with the two ends of the second active layer 161).} disposed on a side of the first light-shielding layer 170 away from the base substrate 101 {figure 3}; wherein the first light-shielding layer 170 is connected to the gate metal layer 162 {Note: the connection of layer 170 to layer 162 is not unlike the connection of the light shielding layer to the gate metal layer in the instant application: indirect.}.; and
the at least one first target transistor 160 further comprises: an active layer 161 and a gate insulating layer 131 { [0139] The first insulating layer 131 is disposed on the first surface 1011 of the base substrate 101 and covers the first active layer 111 to be a gate insulating layer of the first thin film transistor 110.};
wherein the active layer 161, the gate insulating layer 131, the first gate metal layer 162 and the first source/drain metal layer 163 & 164 are sequentially laminated along a direction away from the first light-shielding layer 170 {figure 3}, and an orthographic projection of the active layer 161 on the base substrate 101 falls within an orthographic projection of the first light-shielding layer 170 on the base substrate 101. {figure 3 & Note: the claimed orthographic projections of the layers is not unlike the depicted orthographic projections show in figure 4 of the instant application.}.
As per claim 2 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The gate driving circuit according to claim 1, wherein the conductive material is a metal material {[0059] For example, a metal or metal oxide material or the like may be used to prepare the second light shielding layer 170. }.
As per claim 3 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The gate driving circuit according to claim 1, wherein a thickness of the first light-shielding layer 170 is greater than a thickness threshold {figure 3 & Note: a “thickness threshold” lacks specificity to distinguish over the thickness of layer 170 of the applied prior art.}.
As per claim 9 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The gate driving circuit according to claim 1, wherein the at least one first target transistor 160 further comprises: a buffer layer 134, an interlayer dielectric layer 133 { [0041] The second insulating layer 133 may be made of silicon nitride, silicon oxide, or other suitable materials.} and a passivation layer 135; wherein the buffer layer 134 is disposed between the first light-shielding layer 170 and the active layer 161; the interlayer dielectric layer 133 is disposed between the first source/drain metal layer 163 & 164 and the first gate metal layer 162; and the passivation layer 135 is disposed on a side of the first source/drain metal layer 163 & 164 away from the interlayer dielectric layer 133 {figure 5}.
As per claim 12 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: A method for manufacturing a gate driving circuit, comprising:
forming a first light-shielding layer 170 on a side of a base substrate 101 by using a conductive material {[0059] For example, a metal or metal oxide material or the like may be used to prepare the second light shielding layer 170. }; forming an active layer 161 and a gate insulating layer 131 sequentially on a side of the first light-shielding layer 170 away from the base substrate 101 {figure 5}; and
forming a first gate metal layer 162 { [0053] The second gate electrode 162 may be made of metal, transparent conductive material, or other suitable materials.} and a first source/drain metal layer 163 & 164 { [0055] The second source electrode 163 and the second drain electrode 164 are disposed on the second insulating layer 133 and are electrically connected to the second active layer 161, respectively (for example, the second source electrode 163 and the second drain electrode 164 are disposed directly on two ends of the second active layer 161 and overlap with the two ends of the second active layer 161).} on a side of the gate insulating layer 131 away from the base substrate 101 {figure 3};
wherein the first light-shielding layer 170 is connected to the first gate metal layer 162, and an orthographic projection of the active layer 161 on the base substrate 101 falls within an orthographic projection of the first light-shielding layer 170 on the base substrate 101 {figure 3 & Note: the claimed orthographic projections of the layers is not unlike the depicted orthographic projections show in figure 4 of the instant application.}.
As per claim 13 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The method according to claim 12, further comprising: forming a buffer layer 134 on a side of the active layer 161 away from the base substrate 101, prior to forming the active layer 161 on the side of the first light-shielding layer 170 away from the base substrate 101; forming an interlayer dielectric layer 133 on a side of the first gate metal layer 162 away from the base substrate 101, after forming the first gate metal layer 162 on the side of the gate insulating layer 131 away from the base substrate 101; and forming a passivation layer 135 on a side of the first source/drain metal layer 163 & 164 away from the interlayer dielectric layer 133, after forming the first source/drain metal layer 163 & 164 on the side of the gate insulating layer 131 away from the base substrate 101 {figures 3-7 & Note: the arrangement of the layers shown in figure 3 instruct how the layers are formed on the substrate}.
As per claim 15 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: An array substrate, comprising: a base substrate 101, provided with a display region D2 and a non-display region D1 surrounding the display region D2;
a gate driving circuit disposed in the non-display region D1 { [0058] For example, a gate drive circuit including a plurality of first thin film transistors 110 is provided in the border region D1 & [0062] FIG. 4 is an example circuit diagram of a shift register unit of a gate drive circuit}, and a plurality of pixel circuits disposed in the display region D2 {[0050] The gate drive circuit is located in the border region D1, and the display region D2 includes pixel regions corresponding to pixel units and other components, such as gate lines, data lines, and the like.};
wherein the gate driving circuit comprise a plurality of first transistors 110 { [0038] For example, the gate drive circuit includes a plurality of first thin film transistors 110 as shown in FIG. 1, which are disposed on the first surface 1011 of the base substrate 101.};
wherein at least one first target transistor 160 of the plurality of first transistors 110 comprises: a first light-shielding layer 170 disposed on a side of a base substrate 101, the first light-shielding layer 170 being made of a conductive material {[0059] For example, a metal or metal oxide material or the like may be used to prepare the second light shielding layer 170. }; and
a first gate metal layer 162 { [0053] The second gate electrode 162 may be made of metal, transparent conductive material, or other suitable materials.} and a first source/drain metal layer 163 & 164 { [0055] The second source electrode 163 and the second drain electrode 164 are disposed on the second insulating layer 133 and are electrically connected to the second active layer 161 161, respectively (for example, the second source electrode 163 and the second drain electrode 164 are disposed directly on two ends of the second active layer 161 161 and overlap with the two ends of the second active layer 161 161).} disposed on a side of the first light-shielding layer 170 away from the base substrate 101;
wherein the first light-shielding layer 170 is connected to the first gate metal layer 162 {Note: the connection of layer 170 to layer 162 is not unlike the connection of the light shielding layer to the gate metal layer in the instant application: indirect.}; and
the at least one first target transistor 160 further comprises: an active layer 161 and a gate insulating layer 131 { [0139] The first insulating layer 131 is disposed on the first surface 1011 of the base substrate 101 and covers the first active layer 111 to be a gate insulating layer of the first thin film transistor 110.};
wherein the active layer 161, the gate insulating layer 131, the first gate metal layer 162 and the first source/drain metal layer 163 & 164 are sequentially laminated along a direction away from the first light-shielding layer 170 {figure 3}, and an orthographic projection of the active layer 161 on the base substrate 101 falls within an orthographic projection of the first light-shielding layer 170 on the base substrate 101 {figure 3 & Note: the claimed orthographic projections of the layers is not unlike the depicted orthographic projections show in figure 4 of the instant application.}.
As per claim 16 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The array substrate according to claim 15, wherein each of the pixel circuits comprises a plurality of second transistors, and at least one second target transistor in the plurality of second transistors { [0062] FIG. 4 is an example circuit diagram of a shift register unit of a gate drive circuit. Referring to FIG. 4, the shift register unit 10 and the pixel circuit 20 are disposed together on the base substrate 101. A plurality of gate lines 140 and a plurality of data lines 141 are arranged in an array and intersected with each other to define a plurality of pixel units, each pixel unit comprises at least a basic 2T1C circuit, that is, two transistors T0, N0 and a storage capacitor Cst are utilized to realize the basic function of driving the light emitting element L to emit light.} comprises: a second light-shielding layer 120, a second gate metal layer 112 and a second source/drain metal layer 113/114 sequentially laminated on a side of the base substrate 101 {figure 3}, wherein the second light-shielding layer 120 is made of a conductive material, and the second source/drain metal layer 113/114 comprises a second source pattern and a second drain pattern, the second light-shielding layer 120 being connected to the second source pattern {[0060] For example, the polarizer 150 may be a polyvinyl alcohol (PVA) film prepared by a stretching process or a wire grid obtained by a patterning process, and embodiments of the present disclosure are not limited thereto.}.
As per claim 17 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The array substrate according to claim 16, wherein the plurality of second transistors comprise: a switch transistor T0 and a drive transistor N0; wherein the at least one second target transistor comprises the drive transistor N0 {figure 4}.
As per claim 18 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: A display device, comprising: a source driving circuit 20 and the array substrate as defined in claim 15; wherein the source driving circuit 20 is connected to a data line 141 in the array substrate, and the source driving circuit 20 is configured to provide a data signal for the data line 141 {figure 4}.
As per claim 19 Feng et al discloses, insofar as the claim is sufficiently enabled and definite and understood: The array substrate according to claim 15, wherein the at least one first target transistor 160 further comprises: a buffer layer 134, an interlayer dielectric layer 133 and a passivation layer 135; wherein the buffer layer 134 is disposed between the first light-shielding layer 170 and the active layer 161; the interlayer dielectric layer 133 is disposed between the first source/drain metal layer 163 & 164 and the first gate metal layer 162; and the passivation layer 135 is disposed on a side of the first source/drain metal layer 163 & 164 away from the interlayer dielectric layer 133 {figure 3}.
Allowable Subject Matter
Claims 4-8, 10-11, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the primary reason for the indication of allowable subject is the specific limitations set forth, which include the claimed transistors, pull-up nodes, and the multiple via holes.
Response to Arguments
Applicant's arguments filed May 20, 2026 have been fully considered but they are not persuasive. Applicant asserts in the second full paragraph on page 3 the following: “First of all, Applicant disagrees with the Examiner's opinion on the stacked structure of transistors by combining the gate insulating layer 131 of the first transistor 110 with the constituent structure of the second transistor 160.” The claimed invention does set forth a “stacked structure” and gate insulating layer 131, as shown in figure 3, clearly extends into transistor 160. As a result, it is unclear as to exactly what opinion the applicant disagrees.
Applicant continues to assert in the second full paragraph on page 3 the following: “However, the first insulating layer 131 only functions as the gate insulating layer of the first thin-film transistor 110, rather than a portion of the second thin-film transistor 160.” Even though gate insulating layer 131 “only functions as the gate insulating layer of the first thin-film transistor 110” according to applicant’s assertion, layer 131 does not cease being a “gate insulating layer” and applicant does not require “gate insulating layer” to act with that function with transistor 160. Also, the claimed invention only requires one transistor to include subsequent layers set forth in claim 1.
Applicant further continues to assert in the second full paragraph on page 3 the following:
Secondly, further with reference to FIG. 3 of Feng, for the second transistor 160 associated with the second light-shielding layer 170 in Feng, the second gate electrode 162, the second insulating layer 133, the second active layer 161, the second source electrode 163, and the second drain electrode 164 are sequentially stacked in a direction away from the second light-shielding layer 170. This stacking order is different from the structure defined in amended claim 1, in which the active layer, the gate insulating layer, the first gate metal layer, and the first source/drain metal layer are sequentially stacked in a direction away from the first light-shielding layer.
The claimed invention does not require a specific sequentially stacked order as purported by applicant. Therefore, the applied prior art anticipates the claimed invention as mapped supra, insofar as the claims are sufficiently enabled and definite and understood.
And on page 4 applicant asserts that Feng does not involve the orthographic projection relationship. Applicant’s claimed orthographic projection relationship is not set forth with any specificity to distinguish over the applied prior and the relationship of the applied prior art is not unlike the projections disclosed in the instant application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID D DAVIS whose telephone number is (571)272-7572. The examiner can normally be reached Monday - Friday, 8 a.m. - 4 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID D DAVIS/Primary Examiner, Art Unit 2627
DDD
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