DETAILED ACTION
Claims 1-23 are presented for examination.
Claims 2, 3, 13 are canceled.
Claims 21-23 are new.
This office action is in response to amendment of application on 14-JULY-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to the specification and claim 10 have overcome the objections of the previous office action, and the objections to the specification and claim 10 are withdrawn. Applicant’s amendments to claims 11 and 18 have also overcome the rejections under 35 U.S.C. 112 of the previous office action, and the rejections under 35 U.S.C. 112 are withdrawn. Additionally, since claims 2, 3, 13 were canceled, the corresponding rejections are withdrawn.
Applicant’s arguments, see pages 17-20, filed 14-JULY-2026, with respect to the rejection(s) of claim(s) 1, 12, 17 under 35 U.S.C. 102 and 35 U.S.C. 103 have been fully considered and are persuasive due to amendment. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previously applied prior art references.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Contrary to Applicant’s arguments that Mikami and/or Van Dyke fail to teach or suggest the “routing, in accordance with the interleave map mode, commands for the first portion of the logical address space to the first portion of the physical address space based on the value of the pointer… the routing comprising, for one of the commands, determining a bank select value based on the logical address of the command and the value of the pointer using a modulo operation”, the cited prior art references do teach the limitations. Mikami teaches the elements related to routing commands in an interleave map mode based on the value of a stored boundary address (pointer), a logical address and the physical address it maps to, by determining a bank number (bank select value) and using the value of the pointer. Further, Van Dyke teaches the modulo operation being used to determine a bank select value in an interleaved mode. The combination of the two references teaches all elements of the cited limitations.
By Applicant’s own admission, Van Dyke teaches determining a target partition number based on a modulo operation being performed on physical address bits. With Mikami teaching the physical addresses being used for routing commands, and requiring identifying a page number and a bank number to route commands, the combination of using the particular mechanism involving a modulo operation from Van Dyke to identify the bank number of Mikami is obvious. There is no element in the claims which precludes this combination of determining a bank select value based on the logical address of a command to a physical address of the command, which takes into account a value of a boundary pointer, with a modulo operation.
Nevertheless, since Applicant has amended the claims in a manner that the rejection for Claim 1 must include the references used for the previous rejections for claim 4, the rejections are updated to address the amendments below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22: Claim 22 recites “without using a modulo operation or a division operation”. It is unclear whether this limitation precludes the usage of only one of the two operations, or whether it precludes the usage of both of the operations simultaneously. Therefore, the metes and bounds of the claim limitation are not distinctly set forth, and the claim is rendered indefinite.
For the purposes of examining over prior art, Examiner is interpreting the “without using a modulo operation or a division operation” limitation to only preclude the usage of only one of the two operations. That is, this limitation is interpreted to mean that any routing that does not use the modulo operation and any routing that does not use the division operation both read on the claim limitation under its broadest reasonable interpretation. This interpretation is supported in [0043] of the instant specification, which explicitly distinguishes preceding designs from the present invention by stating that the present invention is directed to the usage of modulo and division operations rather than to XOR operations of the preceding designs, which is interpreted to mean that excluding both the modulo and division operations is not what the present invention is directed to.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 8, 9, 12, 15, 17, 19, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over
Mikami et al., U.S. Pub. No. 20060028880 (hereinafter “Mikami”) in view of
VAN DYKE et al., U.S. Patent No. 8072463 (hereinafter “Van Dyke”).
Regarding claim 1: Mikami teaches a method for configuring logical to physical mapping of a memory comprising multiple banks, the method comprising:
Setting a value of a pointer to define a boundary between a first portion of physical address space of the multiple banks of the memory and a second portion of physical address space of the multiple banks of the memory ([0048] and [0059], Mikami teaches that the system can set setting information which indicates banks to be interleaved, and that the setting information is composed of a boundary address which does the same. Since the banks are physical memory units, the setting of the setting information of Mikami is interpreted to be setting the boundary between the first portion and second portions of the physical address space.)
Mapping, with an interleave map mode, the first portion of logical address space to a portion of physical address space of the multiple banks of the memory; mapping, with a fixed map mode, the second portion of the logical address space to a second portion of the physical address space of the multiple banks of the memory ([0065], Mikami teaches an address conversion table which shows how logical addresses are mapped with physical addresses, and that the physical address specifies a particular bank of memory, which is interpreted as the portions of logical address space mapped to a portion of physical address space of banks of the memory. Furthermore, in [0059-0062], Mikami teaches that the memory can be separated out into interleaved banks and non-interleaved banks, which are interpreted to be the banks mapped with an interleave map mode and banks mapped with a fixed map mode, respectively.).
Routing, in accordance with the interleave map mode, commands for the first portion of the logical address space to the first portion of the physical address space based on the value of the pointer defining the boundary between the first portion of the physical address space and the second portion of the physical address space, the routing comprising, for one of the commands, determining a bank select value based on a logical address of the command and the value of the pointer…; and routing, in accordance with the fixed map mode, other commands for the second portion of the logical address space to the second portion of the physical address space based on a boundary between the first portion of the physical address space and the second portion of the physical address space ([0051-0054], Mikami teaches that the system may receive a data access request, and subsequently convert a logical address of the requested data to a physical address, which is then sent to the memory to store the requested data from the data access request at the address allocated by the memory controller. Furthermore, in [0059-0062], Mikami teaches a boundary address that is placed between the banks which denotes which banks are in a non-interleaved area and which banks are in the interleaved area. Therefore, Mikami teaches routing commands for a portion of logical address space to a portion of physical address space based on a boundary between the portions of the space. Furthermore, in [0082-0091], Mikami teaches a method where the logical addresses of an access request are converted to a physical address based on whether they are meant for the interleave area or non-interleave area. Furthermore, in [0065], Mikami teaches that the physical addresses from the conversion are composed of a bank number (bank select value), which are thus determined based on the logical address and the value of the pointer)
Mikami does not appear to explicitly disclose determining a bank select value… using a modulo operation;
However, Van Dyke teaches determining a bank select value… using a modulo operation; (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation).
Mikami and Van Dyke are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami and Van Dyke to achieve the combined result of determining a bank select value based on a logical address of a command and a value of a pointer, using a modulo operation.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate a translation of a received address to a bank number and bank offset that works for a system in which data is interleaved amongst partitions as discussed in Van Dyke Col. 7 lines 18-41.
Regarding claim 4: The combination of Mikami and Van Dyke teaches all limitations of claim 1, from which claim 4 depends.
Mikami/Van Dyke further teaches determining a bank offset value based on the logical address of the command and the value of the pointer using a division operation. (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation, and determining a RBC address (address inside a bank, interpreted to correspond to the bank offset) using a physical address and a number of partitions in a division operation.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 1.
Regarding claim 5: The combination of Mikami and Van Dyke teaches all limitations of claim 1, from which claim 5 depends.
Mikami/Van Dyke further teaches the first portion of the physical address space mapped with the interleave map aligns with a first subset of the multiple banks of the memory; and the second portion of the physical address space mapped with the fixed map mode aligns with a second subset of the multiple banks of the memory. ([0059], Fig. 2B, and Fig. 7B, Mikami teaches that the boundary address is between the banks denoted as the interleaving area and the non-interleaving area, and explicitly shows the boundary address Ad1 being between banks, which is interpreted as the portions of the physical address space mapped with either map aligning with a first or second subset of the multiple banks of the memory.)
Regarding claim 8: The combination of Mikami and Van Dyke teaches all limitations of claim 5, from which claim 8 depends.
Mikami/Van Dyke further teaches altering the value of the pointer to change a number of banks in the first subset of the banks aligned with the first portion of physical address space mapped with the interleave map mode and another number of banks in the second subset of the banks aligned with the second portion of physical address space mapped with the fixed map mode. ([0062], Mikami teaches the possibility of changing the boundary address, which changes the interleave information that describes which banks are in the non-interleave area and which are in the interleave area, and would thus change a number of banks in the areas.)
Regarding claim 9: The combination of Mikami and Van Dyke teaches all limitations of claim 8, from which claim 9 depends.
Mikami/Van Dyke further teaches remapping a first bank of the memory from the first portion of the physical address space mapped with the interleave map mode to the second portion of the physical address space mapped with the fixed map mode; or remapping a second bank of the memory from the second portion of the physical address space mapped with the fixed map mode to the first portion of the physical address space mapped with the interleave map mode; or ([0062], Mikami teaches that changing the boundary address, results in also changing the interleave information that describes which banks are in the non-interleave area and which are in the interleave area. Given that the boundary specifically defines the separation of banks in the interleave area and in the non-interleave area, the changing of the boundary address is interpreted to cause a bank of one of the area to be remapped to the other area.)
Regarding claim 12: Mikami teaches An apparatus configured to implement hybrid logical to physical memory mapping, the apparatus comprising:
A host interface configured for communication with a host; ([0042-0045], Mikami teaches an OS layer program which receives communications from Applications, and facilitates the processing of requests for them. The Applications are interpreted as a form of a host, and the OS is interpreted as a form of a host interface.)
A media interface configured to enable access to storage media; ([0049-0053], Mikami teaches a controller which interfaces with the memory, and performs functions that facilitate access from a CPU to a memory.)
A processor core configured to execute instructions to manage transfers of data of the host between the host interface and the media interface ([0046-0048], Mikami teaches a CPU which controls programs and executes applications, which also facilitates the sending of requested data to the controller during the execution of certain instructions.)
A memory configured to store the data of the host and data of the processor core; ([0054], Mikami teaches a memory that stores data requested by a data access request (interpreted to be from the host), and is issued by a CPU.)
A memory controller configured to: ([0049-0053], Mikami teaches a controller which interfaces with the memory, and performs functions that facilitate access from a CPU to a memory.)
Set a value of a pointer to define a boundary between a first portion of physical address space of the multiple banks of the memory and a second portion of physical address space of the multiple banks of the memory ([0048] and [0059], Mikami teaches that the system can set setting information which indicates banks to be interleaved, and that the setting information is composed of a boundary address which does the same. Since the banks are physical memory units, the setting of the setting information of Mikami is interpreted to be setting the boundary between the first portion and second portions of the physical address space.)
Map, with an interleave map mode, the first portion of logical address space to a portion of physical address space of the multiple banks of the memory; map, with a fixed map mode, the second portion of the logical address space to a second portion of the physical address space of the multiple banks of the memory ([0065], Mikami teaches an address conversion table which shows how logical addresses are mapped with physical addresses, and that the physical address specifies a particular bank of memory, which is interpreted as the portions of logical address space mapped to a portion of physical address space of banks of the memory. Furthermore, in [0059-0062], Mikami teaches that the memory can be separated out into interleaved banks and non-interleaved banks, which are interpreted to be the banks mapped with an interleave map mode and banks mapped with a fixed map mode, respectively.).
Route, in accordance with the interleave map mode, commands for the first portion of the logical address space to the first portion of the physical address space based on the value of the pointer defining the boundary between the first portion of the physical address space and the second portion of the physical address space, the routing comprising, for one of the commands, determining a bank select value based on a logical address of the command and the value of the pointer…; and route, in accordance with the fixed map mode, other commands for the second portion of the logical address space to the second portion of the physical address space based on a boundary between the first portion of the physical address space and the second portion of the physical address space ([0051-0054], Mikami teaches that the system may receive a data access request, and subsequently convert a logical address of the requested data to a physical address, which is then sent to the memory to store the requested data from the data access request at the address allocated by the memory controller. Furthermore, in [0059-0062], Mikami teaches a boundary address that is placed between the banks which denotes which banks are in a non-interleaved area and which banks are in the interleaved area. Therefore, Mikami teaches routing commands for a portion of logical address space to a portion of physical address space based on a boundary between the portions of the space. Furthermore, in [0082-0091], Mikami teaches a method where the logical addresses of an access request are converted to a physical address based on whether they are meant for the interleave area or non-interleave area. Furthermore, in [0065], Mikami teaches that the physical addresses from the conversion are composed of a bank number (bank select value), which are thus determined based on the logical address and the value of the pointer)
Mikami does not appear to explicitly disclose determining a bank select value… using a modulo operation;
However, Van Dyke teaches determining a bank select value… using a modulo operation; (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation).
Mikami and Van Dyke are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami and Van Dyke to achieve the combined result of determining a bank select value based on a logical address of a command and a value of a pointer, using a modulo operation.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate a translation of a received address to a bank number and bank offset that works for a system in which data is interleaved amongst partitions as discussed in Van Dyke Col. 7 lines 18-41.
Regarding claim 15: The combination of Mikami and Van Dyke teaches all limitations of claim 12, from which claim 15 depends.
Mikami/Van Dyke further teaches bank remap logic configured to: remap a bank of the memory from the first portion of the physical address space mapped with the interleave map mode to the second portion of the physical address space mapped with the fixed map mode; or remap another bank of the memory from the second portion of the physical address space mapped with the fixed map mode to the first portion of the physical address space mapped with the interleave map mode; or ([0062], Mikami teaches that changing the boundary address, results in also changing the interleave information that describes which banks are in the non-interleave area and which are in the interleave area. Given that the boundary specifically defines the separation of banks in the interleave area and in the non-interleave area, the changing of the boundary address is interpreted to cause a bank of one of the area to be remapped to the other area.)
Regarding claim 17: Mikami teaches A System-on-Chip (SoC) configured to implement hybrid logical to physical memory mapping, the SoC comprising:
A component configured to implement a function of the SoC ([0034], Mikami teaches a memory area composed of banks, the memory area being interpreted as the component.)
A processor core configured to execute instructions to manage operation of the SoC; ([0046-0048], Mikami teaches a CPU which controls programs and executes applications, which also facilitates the sending of requested data to the controller during the execution of certain instructions.)
A memory system comprising: a first port configured to enable communication with the processor; a second port configured to enable communication with the component; a memory comprising multiple banks configured to store data of the component and data of the processor core; and a memory controller configured to: ([0049-0054] and [0034], Mikami teaches a memory system which has a memory composed of banks that are configured to store data from a CPU, and has a memory controller which is in communication with the CPU. Since the banks are accessible by the other parts of the memory system, there is interpreted to be a second port configured to enable communication, and since the CPU is in communication with the memory controller of the memory system, there is interpreted to be a first port configured to enable communication with the processor. Furthermore, in [0121], Mikami teaches that a memory component may store the program which performs all of the functions above for managing the memory, which is interpreted to be the data of the component.)
configure a map mode pointer to separate a first region of physical address space of the memory and a second region of physical address space of the memory. ([0048] and [0059], Mikami teaches that the system can set setting information which indicates banks to be interleaved, and that the setting information is composed of a boundary address which does the same. The boundary address being set is interpreted to be the claimed configuring of a pointer that separates regions of the physical address space.)
Map, with an interleave map mode, a first portion of logical address space exposed to the first port and the second port to the first region of physical address space of the memory; map, with a fixed map mode, a second portion of logical address space exposed to the first port and the second port to the second region of physical address space of the memory ([0065], Mikami teaches an address conversion table which shows how logical addresses are mapped with physical addresses, and that the physical address specifies a particular bank of memory, which is interpreted as the portions of logical address space mapped to a portion of physical address space of banks of the memory. Furthermore, in [0059-0062], Mikami teaches that the memory can be separated out into interleaved banks and non-interleaved banks, which are interpreted to be the banks mapped with an interleave map mode and banks mapped with a fixed map mode, respectively.).
Receive commands from the component via the first port or from the processor core via the second port for access to the memory based on a logical address; ([0051-0054], Mikami teaches that the system may receive a data access request, and subsequently convert a logical address of the requested data to a physical address, which is then sent to the memory to store the requested data from the data access request at the address allocated by the memory controller.)
Route, based on the map mode pointer and a logical address of a first command of the commands, the first command to the first region of the physical address space of the memory, the routing of the first command… based on the logical address of the first command and a value of the map mode pointer; and route, based on the map mode pointer and a logical address of a second command of the commands, the second command to the second region of the physical address space of the memory. ([0051-0054], Mikami teaches that the system may receive a data access request, and subsequently convert a logical address of the requested data to a physical address, which is then sent to the memory to store the requested data from the data access request at the address allocated by the memory controller. Furthermore, in [0059-0062], Mikami teaches a boundary address that is placed between the banks which denotes which banks are in a non-interleaved area and which banks are in the interleaved area. Therefore, Mikami teaches routing commands for a portion of logical address space to a portion of physical address space based on a boundary between the portions of the space. Furthermore, in [0082-0091], Mikami teaches a method where the logical addresses of an access request are converted to a physical address based on whether they are meant for the interleave area or non-interleave area. Furthermore, in [0065], Mikami teaches that the physical addresses from the conversion are composed of a bank number (bank select value), which are thus determined based on the logical address and the value of the pointer)
Mikami does not appear to explicitly disclose the routing of the first command comprising using a modulo operation to determine a bank select value
However, Van Dyke teaches the routing of the first command comprising using a modulo operation to determine a bank select value (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation).
Mikami and Van Dyke are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami and Van Dyke to achieve the combined result of determining a bank select value based on a logical address of a command and a value of a pointer, using a modulo operation.
One of ordinary skill in the art would have been motivated to make this modification in order to facilitate a translation of a received address to a bank number and bank offset that works for a system in which data is interleaved amongst partitions as discussed in Van Dyke Col. 7 lines 18-41.
Regarding claim 19: The combination of Mikami and Van Dyke teaches all limitations of claim 17, from which claim 19 depends.
Mikami/Van Dyke further teaches bank remap logic configured to: remap a bank of the memory from the first region of the physical address space mapped with the interleave map mode to the second region of the physical address space mapped with the fixed map mode; or remap another bank of the memory from the second region of the physical address space mapped with the fixed map mode to the first region of the physical address space mapped with the interleave map mode; or ([0062], Mikami teaches that changing the boundary address, results in also changing the interleave information that describes which banks are in the non-interleave area and which are in the interleave area. Given that the boundary specifically defines the separation of banks in the interleave area and in the non-interleave area, the changing of the boundary address is interpreted to cause a bank of one of the area to be remapped to the other area.)
Regarding claim 21: The combination of Mikami and Van Dyke teaches all limitations of claim 17, from which claim 21 depends.
Mikami/Van Dyke further teaches determine, for the first command, a bank offset value based on the logical address of the first command and the value of the map mode pointer using a division operation. (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation, and determining a RBC address (address inside a bank, interpreted to correspond to the bank offset) using a physical address and a number of partitions in a division operation.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 17.
Regarding claim 22: The combination of Mikami and Van Dyke teaches all limitations of claim 17, from which claim 22 depends.
Mikami/Van Dyke further teaches the routing of the second command comprises determining, based on the logical address of the second command, a bank select value and a bank offset value for the second command without using a modulo operation or a division operation. (Col. 5 lines, 50-59, Van Dyke teaches a method of taking only parts of the bits from a virtual address to determine a corresponding physical region (bank select value), as well as different bits from the address to determine a specific byte within that region (bank offset value), which one would recognize is applicable to non-interleaved addresses such as the second portion of logical address space mapped with a non-interleaved mode of Mikami to which the second command is directed to. This is understood to not require a modulo operation or a division operation.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 17.
Regarding claim 23: The combination of Mikami and Van Dyke teaches all limitations of claim 12, from which claim 23 depends.
Mikami/Van Dyke further teaches determine, for the command, a bank offset value based on the logical address of the command and the value of the pointer using a division operation. (Col. 7 line 47 to Col. 8 line 20, Van Dyke teaches a process of determining a partition number from a set of partitions (interpreted to correspond to the bank select value), using a physical address and a number of partitions in a modulo operation, and determining a RBC address (address inside a bank, interpreted to correspond to the bank offset) using a physical address and a number of partitions in a division operation.).
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 23.
Claims 6, 14, 18 are rejected under 35 U.S.C. 103 as being unpatentable over
Mikami et al., U.S. Pub. No. 20060028880 (hereinafter “Mikami”) in view of
VAN DYKE et al., U.S. Patent No. 8072463 (hereinafter “Van Dyke”) further in view of
Nishimori et al., U.S. Pub. No. 20140025867 (hereinafter “Nishimori”).
Regarding claim 6: The combination of Mikami and Van Dyke teaches all limitations of claim 5, from which claim 6 depends.
While Mikami teaches that the categorization of banks also involves a power-saving designation, Mikami/Van Dyke does not appear to explicitly disclose powering down the first subset of the multiple banks aligned with the first portion of the physical address space mapped with the interleave map mode; and powering down at least one bank of the second subset of the multiple banks aligned with the second portion of the physical address space mapped with the fixed map mode.
However, Nishimori teaches powering down the first subset of the multiple banks aligned with the first portion of the physical address space mapped with the interleave map mode; and powering down at least one bank of the second subset of the multiple banks aligned with the second portion of the physical address space mapped with the fixed map mode. ([0035-0037], Nishimori teaches a system with a bank power control functionality that can turn the power supplies for each bank are switched off, which works for all banks in a system with some banks configured for interleaving and some banks configured as non-interleaving.).
Mikami/Van Dyke and Nishimori are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Nishimori to achieve the combined result of a system which powers off the subsets of multiple banks aligned with an interleaved portion and at least one bank of a second subset of multiple banks aligned with a non-interleaved portion.
One of ordinary skill in the art would have been motivated to make this modification in order to save power for banks that are not being used as discussed in Nishimori [0032-0033].
Regarding claim 14: The combination of Mikami and Van Dyke teaches all limitations of claim 12, from which claim 14 depends.
While Mikami teaches that the categorization of banks also involves a power-saving designation, Mikami/Van Dyke does not appear to explicitly disclose power down a first subset of the multiple banks aligned with the first portion of the physical address space mapped with the interleave map mode; and power down at least one bank of a second subset of the multiple banks aligned with the second portion of the physical address space mapped with the fixed map mode.
However, Nishimori teaches power down a first subset of the multiple banks aligned with the first portion of the physical address space mapped with the interleave map mode; and power down at least one bank of a second subset of the multiple banks aligned with the second portion of the physical address space mapped with the fixed map mode. ([0035-0037], Nishimori teaches a system with a bank power control functionality that can turn the power supplies for each bank are switched off, which works for all banks in a system with some banks configured for interleaving and some banks configured as non-interleaving.).
Mikami/Van Dyke and Nishimori are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Nishimori to achieve the combined result of a system which powers off the subsets of multiple banks aligned with an interleaved portion and at least one bank of a second subset of multiple banks aligned with a non-interleaved portion.
One of ordinary skill in the art would have been motivated to make this modification in order to save power for banks that are not being used as discussed in Nishimori [0032-0033].
Regarding claim 18: The combination of Mikami and Van Dyke teaches all limitations of claim 17, from which claim 18 depends.
While Mikami teaches that the categorization of banks also involves a power-saving designation, Mikami/Van Dyke does not appear to explicitly disclose power down a first subset of the multiple banks to which with the first region of the physical address space is mapped with the interleave map mode; and power down at least one bank of a second subset of the banks of the memory to which the second portion of the physical address space is mapped with the fixed map mode.
However, Nishimori teaches power down a first subset of banks aligned with the first region of the physical address space mapped with the interleave map mode; and power down at least one bank of a second subset of the banks of the memory aligned with the second portion of the physical address space mapped with the fixed map mode. ([0035-0037], Nishimori teaches a system with a bank power control functionality that can turn the power supplies for each bank are switched off, which works for all banks in a system with some banks configured for interleaving and some banks configured as non-interleaving.).
Mikami/Van Dyke and Nishimori are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Nishimori to achieve the combined result of a system which powers off the subsets of multiple banks aligned with an interleaved portion and at least one bank of a second subset of multiple banks aligned with a non-interleaved portion.
One of ordinary skill in the art would have been motivated to make this modification in order to save power for banks that are not being used as discussed in Nishimori [0032-0033].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over
Mikami et al., U.S. Pub. No. 20060028880 (hereinafter “Mikami”) in view of
VAN DYKE et al., U.S. Patent No. 8072463 (hereinafter “Van Dyke”) further in view of
Nishimori et al., U.S. Pub. No. 20140025867 (hereinafter “Nishimori”) further in view of
Gonzalez et al., U.S. Pub. No. 20050144361 (hereinafter “Gonzalez”)
Regarding claim 7: The combination of Mikami and Nishimori teaches all limitations of claim 6, from which claim 7 depends.
Mikami/Van Dyke/Nishimori further teaches the at least one bank of the second subset of the multiple banks comprises a first bank of the second subset of the multiple banks ([0059-0061] and Fig. 2B, Mikami teaches a subset of the banks that are non-interleaved, which are interpreted as the claimed second subset, which contains the bank Bank 0.)
Mikami/Van Dyke/Nishimori further teaches powering down at least one of the instances of the second bank ([0035-0037], Nishimori teaches that banks can be set to be powered down individually, which could include powering down at least one instance of the second bank.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 6.
While Nishimori teaches settings being set dynamically for individual banks, Mikami/Van Dyke/Nishimori does not appear to explicitly disclose reconfiguring instances of a second bank of the second subset of the multiple banks from a parallel access mode to a sequential access mode
However, Gonzalez teaches reconfiguring instances of a metablock from a parallel access mode to a sequential access mode. ([0015], Gonzalez teaches that parallel programming to a metablock may be converted to sequential programming when data writes to the metablock have changed such that it would improve performance.).
Mikami/Van Dyke/Nishimori and Gonzalez are analogous art because they are from the same field of endeavor, memory mapping schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke/Nishimori and Gonzalez to achieve the combined result of a system with banks that can individually turn off, which may convert parallel programming to a bank to sequential programming to the bank.
One of ordinary skill in the art would have been motivated to make this modification in order to optimize memory utilization according to usage patterns for a memory location, as discussed in Gonzalez [0038].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over
Mikami et al., U.S. Pub. No. 20060028880 (hereinafter “Mikami”) in view of
VAN DYKE et al., U.S. Patent No. 8072463 (hereinafter “Van Dyke”) further in view of
Springberg, U.S. Pub. No. 20200065204 (hereinafter “Springberg”).
Regarding claim 10: The combination of Mikami and Van Dyke teaches all limitations of claim 9, from which claim 10 depends.
While Mikami teaches a remapping of banks from an interleave mode to a non-interleave mode, Mikami/Van Dyke does not appear to explicitly disclose the first bank of the memory is remapped to the second portion of the physical address space mapped with the fixed map mode in response to determining that a location within the first bank of the memory is defective, and the method further comprises: altering an available physical address range of the first bank of the memory to prevent access to the location within the first bank of the memory that is defective.
However, Springberg teaches the first bank of the memory is remapped to the second portion of the physical address space mapped with the fixed map mode in response to determining that a location within the first bank of the memory is defective, and the method further comprises: altering an available physical address range of the first bank of the memory to prevent access to the location within the first bank of the memory that is defective. ([0021-0025], Springberg teaches a method for dealing with a striped (ie. interleaved) memory space, wherein when a failure is detected on a portion of a memory component that is part of the striping scheme, the system can move the failed portion to a recovery portion on a different memory component, which is interpreted as the remapping to a second portion of the physical address space in response to determining that a location in the component is defective. Furthermore, in [0026-0027], Springberg teaches that the recovery portion is considered to be outside of the accessible range, which prevents the host system from accessing the data, and since it is described as moving to a single portion in a single component not used in the striping scheme (instead of also being striped across all the components like the host data is), it is interpreted as a non-interleaved address space.)
Mikami/Van Dyke and Springberg are analogous art because they are from the same field of endeavor, memory management schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Springberg to achieve the result of a system which may remap a bank with a detected defect to a portion of physical address space mapped with a non-interleaved mode and altering an available physical address range of the bank to prevent access to the location within the bank that is defective.
One of ordinary skill in the art would have been motivated to make this modification in order to recover data that is otherwise failed, in a system with interleaved components, as discussed in Springberg [0030-0035].
Claims 11, 16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over
Mikami et al., U.S. Pub. No. 20060028880 (hereinafter “Mikami”) in view of
VAN DYKE et al., U.S. Patent No. 8072463 (hereinafter “Van Dyke”) further in view of
Sharon et al., U.S. Pub. No. 20140006898 (hereinafter “Sharon”)
Regarding claim 11: The combination of Mikami and Van Dyke teaches all limitations of claim 1, from which claim 11 depends.
While Mikami teaches an arbitrary dividing of the physical address space to be configured for different kinds of properties simultaneously, Mikami/Van Dyke does not appear to explicitly disclose dividing the physical address space of the multiple banks of the memory into a third portion of the physical address space and a fourth portion of the physical address space; configuring the third portion of the physical address space for a first type of error and data correction; configuring the fourth portion of the physical address space for a second type of error and data correction; and performing, based on respective logical addresses of the commands or the other commands, a first type of error and data correction or the second type of error and data correction on respective data of the commands or the other commands.
However, Sharon teaches dividing the physical address space of the multiple banks of the memory into a third portion of the physical address space and a fourth portion of the physical address space; configuring the third portion of the physical address space for a first type of error and data correction; configuring the fourth portion of the physical address space for a second type of error and data correction; and performing, based on respective logical addresses of the commands or the other commands, a first type of error and data correction or the second type of error and data correction on respective data of the commands or the other commands. ([0028-0032] and [0023], Sharon teaches a system with multiple partitions of the physical address space that can be entire components of the memory, wherein the partitions each have different types of ECC protection, which is interpreted to be dividing the physical address space of multiple components of the memory into a third and fourth portion, each configured with a different type of error and data correction. Furthermore, in the same paragraphs, Sharon also teaches that different kinds of ECC algorithms are performed on the data within the different partitions.)
Mikami/Van Dyke and Sharon are analogous art because they are from the same field of endeavor, memory management schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Sharon to achieve the result of a system which divides the physical memory space into partitions with different types of ECC protection, and performs a first or second type of error correction according to what kinds of logical addresses of previous commands were routed to the partitions.
One of ordinary skill in the art would have been motivated to make this modification in order to optimize the kind of ECC protection scheme applied to distinct kinds of access patterns, as discussed in Sharon [0024-0027].
Regarding claim 16: The combination of Mikami and Van Dyke teaches all limitations of claim 12, from which claim 16 depends.
While Mikami teaches an arbitrary dividing of the physical address space to be configured for different kinds of properties simultaneously, Mikami/Van Dyke does not appear to explicitly disclose error detection and correction logic configured to: divide the physical address space of the multiple banks of the memory into a third portion of the physical address space and a fourth portion of the physical address space; configure the third portion of the physical address space for a first type of error and data correction; configure the fourth portion of the physical address space for a second type of error and data correction; and perform, based on respective logical addresses of the command or the other commands, a first type of error and data correction or the second type of error and data correction on respective data of the commands or the other commands.
However, Sharon teaches error detection and correction logic configured to: divide the physical address space of the multiple banks of the memory into a third portion of the physical address space and a fourth portion of the physical address space; configure the third portion of the physical address space for a first type of error and data correction; configure the fourth portion of the physical address space for a second type of error and data correction; and perform, based on respective logical addresses of the command or the other commands, a first type of error and data correction or the second type of error and data correction on respective data of the commands or the other commands. ([0028-0032] and [0023], Sharon teaches a system with multiple partitions of the physical address space that can be entire components of the memory, wherein the partitions each have different types of ECC protection, which is interpreted to be dividing the physical address space of multiple components of the memory into a third and fourth portion, each configured with a different type of error and data correction. Furthermore, in the same paragraphs, Sharon also teaches that different kinds of ECC algorithms are performed on the data within the different partitions.)
Mikami/Van Dyke and Sharon are analogous art because they are from the same field of endeavor, memory management schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Sharon to achieve the result of a system which divides the physical memory space into partitions with different types of ECC protection, and performs a first or second type of error correction according to what kinds of logical addresses of previous commands were routed to the partitions.
One of ordinary skill in the art would have been motivated to make this modification in order to optimize the kind of ECC protection scheme applied to distinct kinds of access patterns, as discussed in Sharon [0024-0027].
Regarding claim 20: The combination of Mikami and Van Dyke teaches all limitations of claim 19, from which claim 20 depends.
While Mikami teaches an arbitrary dividing of the physical address space to be configured for different kinds of properties simultaneously, Mikami/Van Dyke does not appear to explicitly disclose error detection and correction logic configured to: divide the physical address space of the multiple banks of the memory into a third region of the physical address space and a fourth region of the physical address space; configure the third region of the physical address space for a first type of error and data correction; configure the fourth region of the physical address space for a second type of error and data correction; and perform, based on the logical address of a command, a first type of error and data correction or the second type of error and data correction on data of the command.
However, Sharon teaches error detection and correction logic configured to: divide the physical address space of the multiple banks of the memory into a third region of the physical address space and a fourth region of the physical address space; configure the third region of the physical address space for a first type of error and data correction; configure the fourth region of the physical address space for a second type of error and data correction; and perform, based on the logical address of a command, a first type of error and data correction or the second type of error and data correction on data of the command. ([0028-0032] and [0023], Sharon teaches a system with multiple partitions of the physical address space that can be entire components of the memory, wherein the partitions each have different types of ECC protection, which is interpreted to be dividing the physical address space of multiple components of the memory into a third and fourth portion, each configured with a different type of error and data correction. Furthermore, in the same paragraphs, Sharon also teaches that different kinds of ECC algorithms are performed on the data within the different partitions.)
Mikami/Van Dyke and Sharon are analogous art because they are from the same field of endeavor, memory management schemes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Mikami/Van Dyke and Sharon to achieve the result of a system which divides the physical memory space into partitions with different types of ECC protection, and performs a first or second type of error correction according to what kinds of logical addresses of previous commands were routed to the partitions.
One of ordinary skill in the art would have been motivated to make this modification in order to optimize the kind of ECC protection scheme applied to distinct kinds of access patterns, as discussed in Sharon [0024-0027].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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