Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation “fifth transistor" and “sixth transistor” without claiming a third and fourth transistor. It is unclear whether third and fourth transistors are requires and thus there is insufficient antecedent basis for this limitation in the claim. As best understood and for purposes of this office action it will be interpreted as similar to the third and fourth transistors in Claim 4 (i.e., an inverter comprised of two transistors).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujikawa (US App. 20210278735 hereinafter referred to as “Fuji”) in view of Zhou et al. (US App. 20220301499).
In regards to claim 1, Fuji teaches an electro-optical device (see at least Abstract) comprising: data lines grouped into a set of k, k being an integer of two or more (see Fig.3); a data signal line to which a data signal is output, the data signal corresponding to a gray scale of a pixel and corresponding to the group of each set of k (see Para. 7); and transmission gates provided in a one-to-one correspondence with the data lines, wherein an input end of the transmission gate is coupled to the data signal line, an output end of the transmission gate is coupled to the data line (see Fig. 3, Item 152), a conductive state between the input end and the output end is defined based on a positive logic selection signal and a negative logic selection signal, the transmission gate includes a first transistor of a first conductivity type having a gate node to which the positive logic selection signal is supplied, and a second transistor of a second conductivity type having a gate node to which the negative logic selection signal is supplied, the data lines include a first data line and a second data line adjacent to the first data line in a first direction, the transmission gates include a first transmission gate provided corresponding to the first data line and a second transmission gate provided corresponding to the second data line (see Fig. 3, Item 152 applied to each data line and comprised of n-type and p-type transistors), when an array direction of the data lines is the first direction, the first transistor of the first transmission gate is adjacent to the second transistor of the second transmission gate in the first direction, the second transistor of the first transmission gate is adjacent to the first transistor of the second transmission gate in the first direction (see Fig. 3).
Fuji is not relied upon to teach and a channel length of the first transistor is different from a channel length of the second transistor.
However, Zhou teaches and a channel length of the first transistor is different from a channel length of the second transistor (see Figs. 6, 7, 12, and Para. 73 channel lengths designed to be different).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou for voltage compensation (See Para. 4). Examiner also notes Fuji discloses the base product/process of two transistors connected to the data line while Zhou teaches the known technique of different channel lengths so as to yield predictable results of two transistors of two lengths on the data lines in the device of Fuji.
Regarding claim 2, Fuji in view of Zhou teaches all the limitations of claim 1. Zhou further teaches wherein the channel length of the first transistor is shorter than the channel length of the second transistor (see Figs. 6, 12, and Para. 73 channel lengths designed to be different).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou for voltage compensation (See Para. 4). Examiner also notes Fuji discloses the base product/process of two transistors connected to the data line while Zhou teaches the known technique of different channel lengths so as to yield predictable results of two transistors of two lengths on the data lines in the device of Fuji.
Regarding claim 3, Fuji in view of Zhou teaches all the limitations of claim 1. Fuji further teaches wherein when an extending direction of the data line is a second direction, the first transistor and the second transistor of the first transmission gate corresponding to the first data line are disposed along the second direction, and the second transistor and the first transistor of the second transmission gate corresponding to the second data line are disposed along the second direction (see Fig. 3, one n-type and p-type for each data line).
Regarding claim 6, Fuji in view of Zhou teaches all the limitations of claim 1. Fuji further teaches an electronic apparatus comprising the electro-optical device according to claim 1 (See Title).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujikawa (US App. 20210278735 hereinafter referred to as “Fuji”) in view of Zhou et al. (US App. 20220301499) in further view of Kubota et al. (US App. 20060158395) and Electrical Engineering (“Implementation of a NOT gate with two transistors - Whynot one?”; https://electronics.stackexchange.com/questions/167250/implementation-of-a-not-gate-with-two-transistors-why-not-one; May 2015).
Regarding claim 4, Fuji in view of Zhou teaches all the limitations of claim 1. Fuji and Zhou are not relied upon to teach comprising a first NOT circuit configured to supply the positive logic selection signal to the gate node of the first transistor, wherein the first NOT circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third transistor of the first NOT circuit corresponding to the first data line is adjacent, in the first direction, to the fourth transistor of the first NOT circuit corresponding to the second data line, and the fourth transistor of the first NOT circuit corresponding to the first data line is adjacent, in the first direction, to the third transistor of the first NOT circuit corresponding to the second data line.
However, Kubota teaches comprising a first NOT circuit configured to supply the positive logic selection signal to the gate node of the first transistor, (see Fig. 3, 32); corresponding to the first data line is adjacent; corresponding to the second data line, corresponding to the first data line is adjacent, in the first direction, (see Fig. 3 inverters in each column).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou inverters of Kubota to control grayscale to data lines properly (See Para. 8).
Fuji in view of Zhou and Kubota are not relied upon to teach wherein the first NOT circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third transistor of the first NOT circuit, in the first direction, to the fourth transistor of the first NOT circuit and the fourth transistor of the first NOT circuit to the third transistor of the first NOT circuit.
However, EE teaches wherein the first NOT circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third transistor of the first NOT circuit, in the first direction, to the fourth transistor of the first NOT circuit and the fourth transistor of the first NOT circuit to the third transistor of the first NOT circuit (see Page 1, inverter is comprised of two opposite types of transistors).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou inverters of Kubota with inverter design of EE as a well known technique to yield predictable results of improved switching with less noise in the display of Fuji as modified by Zhou and Kubota under MPEP 2143.
Regarding claim 5, Fuji in view of Zhou teaches all the limitations of claim 1. Fuji and Zhou are not relied upon to teach comprising a second NOT circuit configured to supply the negative logic selection signal to the gate node of the second transistor, wherein the second NOT circuit includes a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor of the second NOT circuit corresponding to the first data line is adjacent, in the first direction, to the sixth transistor of the second NOT circuit corresponding to the second data line, and the sixth transistor of the second NOT circuit corresponding to the first data line is adjacent, in the first direction, to the fifth transistor of the second NOT circuit corresponding to the second data line.
However, Kubota teaches comprising a second NOT circuit configured to supply the negative logic selection signal to the gate node of the second transistor (see Fig. 3, 32); corresponding to the first data line is adjacent, in the first direction, corresponding to the second data line, corresponding to the first data line is adjacent, in the first direction, corresponding to the second data line (see Fig. 3 inverters in each column).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou inverters of Kubota to control grayscale to data lines properly (See Para. 8).
Fuji in view of Zhou and Kubota are not relied upon to teach wherein the second NOT circuit includes a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor of the second NOT circuit to the sixth transistor of the second NOT circuit and the sixth transistor of the second NOT circuit to the fifth transistor of the second NOT circuit
However, EE teaches wherein the second NOT circuit includes a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor of the second NOT circuit to the sixth transistor of the second NOT circuit and the sixth transistor of the second NOT circuit to the fifth transistor of the second NOT circuit (see Page 1, inverter is comprised of two opposite types of transistors).
It would have been obvious to a person of ordinary skill in the art to modify the transistors of Fuji with different channel lengths of Zhou inverters of Kubota with inverter design of EE as a well known technique to yield predictable results of improved switching with less noise provided in the display of Fuji as modified by Zhou and Kubota under MPEP 2143.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes: Nakagawa (US APP. 20130082915) describing transistors in series with each data line, and Fig. 3 of Aoki (US Pat. 5309151) disclosing two transistors per column and an inverter controlling one transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW YEUNG whose telephone number is (571)272-4115. The examiner can normally be reached M-F 9am-5pm EST.
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/MATTHEW YEUNG/Primary Examiner, Art Unit 2625
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