DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4-7 is/are rejected under 35 U.S.C. 102a2 as being anticipated by US Patent Pub. 2021/0193053 A1 to Ota et al (“Ota”).
As to claim 1, Ota discloses a display device (See Fig. 2-4), comprising:
a scanning line (12);
a data line (14a-b);
a pixel circuit (110) provided corresponding to the scanning line and the data line; and
a data potential generating circuit (See Fig. 2, 30) configured to generate a data potential, wherein
the pixel circuit (See Fig. 4) includes a first transistor (121), a second transistor (122), a third transistor (123/125), a fourth transistor (124), and a light-emitting element (130),
the first transistor having a first gate, a first drain, and a first source (See Fig. 4),
the first transistor supplies a current in accordance with a voltage between the first gate and the first source to the light-emitting element (See Fig. 4; The first transistor supplies a current from the power supply line 116 to the light emitting element 130.),
the second transistor controls electrical coupling between the data line and the first gate in accordance with a potential of the scanning line (See Fig. 4; Transistor 122 is coupled to the gate of the transistor 121.),
the third transistor controls electrical coupling between the data line and the first drain (See Fig. 4; Transistors 123 are coupled to data line 14b.),
the fourth transistor controls electrical coupling between the light-emitting element and the first drain (See Fig. 4; Transistor 124 is coupled to the light emitting element 130.),
in a first period,
the second transistor is on, the third transistor and the fourth transistor are off, and the first gate is supplied with a predetermined first potential via the data line (See Fig. 4 and 5; During period A, Gwr(i) is turned ON and Gcmp(i) and Gel(i) are turned OFF.),
in a second period after the first period,
the second transistor and the third transistor are on, the fourth transistor is off, and the data line and the first gate and the first drain are electrically coupled to each other (See Fig. 4 and 5; During period B, Gwr(i) and Gcmp(i) are turned ON and Gel(i) are turned OFF.), and
in a third period after the second period,
the second transistor is on, the third transistor and the fourth transistor are off, and the first gate is supplied with the data potential via the data line and the second transistor (See Fig. 4 and 5; During period C, Gwr(i) is turned ON and Gcmp(i) and Gel(i) are turned OFF.).
As to claim 4, Ota discloses comprising:
a data supply line (Fig. 3, Vd(1), Vd(2), Vd(3)) to which the data potential generated by the data potential generating circuit is supplied; and
a switch circuit (Fig. 3, 40, 45) configured to control electrical coupling between the data line and the data supply line, wherein
in the first period and the second period, the switch circuit is off, and
in the third period, the switch circuit is on, and the data potential output from the data potential generating circuit is transferred from the data supply line to the data line.
As to claim 5, Ota discloses wherein the data potential generating circuit includes an amplifier circuit (See Fig. 2, 34).
As to claim 6, Ota discloses (See Fig. 3) comprising:
a data supply line (Vd(1), Vd(2), Vd(3)) to which the data potential generated by the data potential generating circuit is supplied;
a data transfer line (14a);
a capacitance element (61) coupled to the data transfer line;
a first switch circuit (72) configured to control electrical coupling between the data line and the data transfer line; and
a second switch circuit (45) configured to control electrical coupling between the data transfer line and the data supply line, wherein
in the first period and the second period, the first switch circuit is off (See Fig 5; Gcp is turned OFF during periods A and B.),
in the first period and the third period, the second switch circuit is off (See Fig. 5, Sel (1-q) are turned OFF during periods A and C.),
in a period overlapping a part of the second period, the second switch circuit is on, the data potential output from the data potential generating circuit is transferred from the data supply line to the data transfer line, and the data potential transferred to the data transfer line is held in the capacitance element (See Fig. 5, ¶ 0065, 0107; The second switches Sel(1-q) are turned ON during a second period where data potentials Vd(1), Vd(2) and Vd(3) are transferred to the data supply lines 14A and held by the capacitive element 61.), and
in the third period, the first switch circuit is on, and the data potential held in the capacitance element is supplied to the first gate (See Fig. 5; Gcp is turned on during period C.).
As to claim 7, Ota discloses wherein
in a fourth period after the third period (See Fig. 5, D),
the second transistor and the third transistor are off, the fourth transistor is on, a current flowing from the source to the first drain is supplied to the light-emitting element via the fourth transistor, and the light-emitting element emits light (See Fig. 4 and 5; During period C, Gwr(i) and Gcmp(i) are turned OFF and Gel(i) is turned ON.).
As to claim 8, the same rejection or discussion is used as in the rejection of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Pub. 2021/0193053 A1 to Ota et al (“Ota”) in view of US Patent Pub. 2022/0413328 A1 to Koga.
As to claim 2, Ota discloses wherein the data potential generating circuit includes a DAC that outputs the data potential (See Fig. 2, 33), fails to disclose wherein the data potential generating circuit includes a capacitive DAC.
Koga discloses wherein the data potential generating circuit includes a capacitive DAC (¶ 0191).
Before the effective filing date, it would have been obvious to one of ordinary skill in the art to have modified Ota with the teachings of Koga wherein the data potential generating circuit includes a capacitive DAC, as suggested by Koga thereby similarly using known configurations for providing capacitance DAC for performing digital/analog conversion.
As to claim 3, Ota in view of Koga discloses wherein in the second period an output node of the capacitive DAC is supplied with a predetermined second potential (Ota; See Fig. 5; The data supply lines Vd(1), Vd(2), Vd(3) which are the outputs of the DAC 33 (Fig. 2) supply data voltages during the compensation period B. Koga discloses the limitations regarding the capacitive DAC in the rejection of claim 2.).
Conclusion
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/NICHOLAS J LEE/Primary Examiner, Art Unit 2624