DETAILED ACTION
Claims 1-17 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claim 1 is an independent claims. Claims 2-17 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 02-26-2025.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. It is also noted, that applicant has filed a certified copy on 08-05-2025 as required by 35 U.S.C. 119(b).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02-26-2025 is in compliance with the provisions of 37 CFR 1.97
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-16 are rejected under 35 U.S.C. 102(a)(1)/(a)/(2) as being anticipated by U.S. Publication No. 2008/0028249 (hereinafter, “Agrawal”).
As per claim 1, Agrawal discloses a clock frequency regulating circuit, comprising:
a memory circuit configured to store data according to an input clock and output the data according to an output clock; (inter alia: system comprising a first FIFO 203A to store data by operating its clock in the first domain and a second FIFO for outputting data by operating its clock in different clock domain; ¶s [0024]-[0037])
a frequency detection circuit coupled with the memory circuit, the frequency detection circuit configured to detect a variation in a used amount of a storage space of the memory circuit and accordingly generate a frequency detection result; and (trigger generator coupled to FIFOs by receiving “almost_full” signal to indicate “buffer occupancy”, ( See ¶s [0027]-[0030] ) and based on that, the system is capable “to change the frequency of the processing unit which has to read and process the data stored in this FIFO buffer” ¶ [0031])
a clock management unit (CMU) coupled with the frequency detection circuit, the CMU configured to regulate a frequency of the output clock according to the frequency detection result. (¶ [0033] discloses how a frequency selector (103) selects one of these frequencies based on some control signals generated by a control block (104). The selected frequency is shown as f in FIG. 4.)
Agrawal discloses the following: (Emphasis added by the Office)
“The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments of the present invention allow the processing unit to use the maximum possible clock frequency only when it is required and run at some lower frequencies in low processing power requirements…………………….
a system for adaptive frequency scaling in an electronic device includes an input interface block for receiving real time data, at least one processing unit for processing real time data received by the input interface block, at least one memory unit for storing the real time data before the data is processed by the processing unit, a frequency divider block for generating multiple clock frequencies from received clock frequency; and a control unit for selecting the appropriate frequency of operation from the multiple clock frequencies wherein the selection is based on the level of utilization of the memory unit.” ¶s [0013]-[0014]
As per claim 2, Agrawal discloses the clock frequency regulating circuit, wherein after the memory circuit stores the data for a period of time according to the input clock, the frequency detection circuit starts detecting the variation in the used amount of the storage space of the memory circuit. (the system is configured to measure the occupancy status (e.g., fullness) of the memory buffer, and based on that measurement, a “bit can be asserted at a time” ¶s [0027]-[0031]. Stated differently, the bit signal is a measure how full is the memory buffer during the time of measurement that causes frequency change at that time. ¶s [0027]-[0034] )
As per claim 3, Agrawal discloses the clock frequency regulating circuit, wherein the frequency detection circuit determines which of a plurality of variation intervals the variation falls within; (¶ [0027] states “almost_full[2]=1, if buffer occupancy is between 75% and 100” )
when the variation falls within a first variation interval of the plurality of variation intervals, the frequency detection circuit generates the frequency detection result to request the CMU to regulate the frequency of the output clock according to a first degree of adjustment; and (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
when the variation falls within a second variation interval of the plurality of variation intervals, the frequency detection circuit generates the frequency detection result to request the CMU to regulate the frequency of the output clock according to a second degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 4, Agrawal discloses the clock frequency regulating circuit wherein when the variation falls within the first variation interval, the frequency detection circuit generates the frequency detection result to request the CMU to increase the frequency of the output clock according to the first degree of adjustment; and when the variation falls within the second variation interval, the frequency detection circuit generates the frequency detection result to request the CMU to decrease the frequency of the output clock according to the second degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 5, Agrawal discloses the clock frequency regulating circuit wherein the first degree of adjustment is different from the second degree of adjustment. (¶ [005] discloses how the technique enables a chip to operate at different voltages and clock frequencies)
As per claim 6, Agrawal discloses the clock frequency regulating circuit further comprising: a water-level detection circuit coupled to the memory circuit and the CMU, the water-level detection circuit configured to detect the used amount of the storage space of the memory circuit and thereby generate a water-level detection result, wherein the CMU is further configured to regulate the frequency of the output clock according to the water-level detection result. ( ¶s [0013]-[0014] state where “The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments of the present invention allow the processing unit to use the maximum possible clock frequency only when it is required and run at some lower frequencies in low processing power requirements & a system for adaptive frequency scaling in an electronic device includes an input interface block for receiving real time data, at least one processing unit for processing real time data received by the input interface block, at least one memory unit for storing the real time data before the data is processed by the processing unit, a frequency divider block for generating multiple clock frequencies from received clock frequency; and a control unit for selecting the appropriate frequency of operation from the multiple clock frequencies wherein the selection is based on the level of utilization of the memory unit.”
As per claim 7, Agrawal discloses the clock frequency regulating circuit wherein after the memory circuit stores the data for a period of time according to the input clock, the water-level detection circuit starts detecting the used amount of the storage space of the memory circuit. ( ¶s [0013]-[0014] state where “The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments of the present invention allow the processing unit to use the maximum possible clock frequency only when it is required and run at some lower frequencies in low processing power requirements & a system for adaptive frequency scaling in an electronic device includes an input interface block for receiving real time data, at least one processing unit for processing real time data received by the input interface block, at least one memory unit for storing the real time data before the data is processed by the processing unit, a frequency divider block for generating multiple clock frequencies from received clock frequency; and a control unit for selecting the appropriate frequency of operation from the multiple clock frequencies wherein the selection is based on the level of utilization of the memory unit.”
As per claim 8, Agrawal discloses the clock frequency regulating circuit wherein the water-level detection circuit determines which of a plurality of water-level intervals the used amount falls within; when the used amount falls within a first water-level interval of the plurality of water-level intervals, the water-level detection circuit generates the water-level detection result to request the CMU to regulate the frequency of the output clock according to a third degree of adjustment; and when the used amount falls within a second water-level interval of the plurality of water-level intervals, the water-level detection circuit generates the water-level detection result to request the CMU to regulate the frequency of the output clock according to a fourth degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 9, Agrawal discloses the clock frequency regulating circuit, wherein when the used amount falls within the first water-level interval, the water-level detection circuit generates the water-level detection result to request the CMU to increase the frequency of the output clock according to the third degree of adjustment; and when the used amount falls within the second water-level interval, the water-level detection circuit generates the water-level detection result to request the CMU to decrease the frequency of the output clock according to the fourth degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 10, Agrawal discloses the clock frequency regulating circuit wherein the third degree of adjustment is different from the fourth degree of adjustment. (¶s [0027]-[0030] discloses how based on plurality of occupancy level of memory, clock frequency may be adjusted. Therefore, the Office submits that it would apparent to one having ordinary skill in the art to scale the number of occupancy ranges for which frequency may be scaled. )
As per claim 11, Agrawal discloses the clock frequency regulating circuit wherein a total number of the plurality of water-level intervals is less than a total number of the plurality of variation intervals. (¶s [0027]-[0030] discloses how based on plurality of occupancy level of memory, clock frequency may be adjusted. Therefore, the Office submits that it would apparent to one having ordinary skill in the art to scale the number of occupancy ranges for which frequency may be scaled. )
As per claim 12, Agrawal discloses the clock frequency regulating circuit further comprising: a water-level detection circuit coupled to the memory circuit and the CMU, the water-level detection circuit configured to detect the used amount of the storage space of the memory circuit and thereby generate a water-level detection result, wherein the CMU is further configured to regulate the frequency of the output clock according to the water-level detection result. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 13, Agrawal discloses the clock frequency regulating circuit wherein after the memory circuit stores the data for a period of time according to the input clock, the water-level detection circuit starts detecting the used amount of the storage space of the memory circuit. (the system is configured to measure the occupancy status (e.g., fullness) of the memory buffer, and based on that measurement, a “bit can be asserted at a time” ¶s [0027]-[0031]. Stated differently, the bit signal is a measure how full is the memory buffer during the time of measurement that causes frequency change at that time. ¶s [0027]-[0034] )
As per claim 14, Agrawal discloses the clock frequency regulating circuit wherein the water-level detection circuit determines which of a plurality of water-level intervals the used amount falls within;when the used amount falls within a first water-level interval of the plurality of water-level intervals, the water-level detection circuit generates the water-level detection result to request the CMU to regulate the frequency of the output clock according to a first degree of adjustment; and when the used amount falls within a second water-level interval of the plurality of water-level intervals, the water-level detection circuit generates the water-level detection result to request the CMU to regulate the frequency of the output clock according to a second degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 15, Agrawal discloses the clock frequency regulating circuit wherein when the used amount falls within the first water-level interval, the water-level detection circuit generates the water-level detection result to request the CMU to increase the frequency of the output clock according to the first degree of adjustment; and when the used amount falls within the second water-level interval, the water-level detection circuit generates the water-level detection result to request the CMU to decrease the frequency of the output clock according to the second degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
As per claim 16, Agrawal discloses the clock frequency regulating circuit wherein the first degree of adjustment is different from the second degree of adjustment. (¶ [0032] states “The frequency of the processing unit in embodiments of the present invention is changed on the basis of the change in workload. The workload is estimated on the basis of the amount of data in the memory waiting to be processed by the processing unit. This is predicted by checking the status of "almost_full" signal. Whenever the value of the signal "almost_full" changes, the algorithm changes the frequency of the processing unit. This means that the performance of the algorithm is highly dependent on the definition and the structure of the signal "almost_full" since it represents different memory occupancy levels. Whenever any change is detected in "almost_full", it triggers the algorithm to change the frequency of the processing unit. For the structure and definition of the "almost_full" signal described above, the frequency of the processing unit changes only when the memory occupancy level reaches 25%, 50% or 75%. The frequency would not get changed for any other changes in the memory occupancy level because the algorithm is dependent on the structure of "almost_full" signal and according to the above defined definition, the value of "almost_full" signal changes only when the memory occupancy reaches 25%, 50% or 75%. The value of the "almost_full" signal will remain the same for other changes in the memory occupancy.” )
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2008/0028249 (hereinafter, “Agrawal”) in view of Admitted Prior Art (hereinafter, “Admitted Prior Art” ).
As per claim 17, Agrawal disclose the clock frequency regulating circuit. (Fig’s 1-6)
Agrawal does not disclose wherein the clock frequency regulating circuit is applied to a retimer.
However, Admitted Prior Art explicitly discloses wherein the clock frequency regulating circuit is applied to a retimer. (¶s [002]-[004] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Agrawal and Admitted Prior Art because both references are in the same field of endeavor. Admitted Prior Art’s teaching of retimer would enhance Agrawal 's system by synchronizing clocks between transmitter circuits and receiver circuits, thus eliminating degradation, further enhancing data communication.
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
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