DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/26/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: The emitters and collectors of the PNP transistors are referred to incorrectly throughout the specification. The collector of the PNP transistors are referred to as the emitter and the emitter of the PNP transistors are referred to as the collector.
Appropriate correction is required.
Claim Objections
Claim 2 is objected to because of the following informalities: The emitter and collector of the PNP transistor (i.e. first transistor (Q1_f) is referred to incorrectly. The collector of the PNP transistor is referred to as the emitter and the emitter is referred to as the collector. Based on the drawings filed 02/26/2025, the emitter of the first transistor is connected to the input terminal and the collector of the first transistor is connected to the base of the second transistor (refer to the drawing below and Wikipedia “Bipolar junction transistor”). Appropriate correction is required. For the purposes of examination, Claim 2 is interpreted to recite: The TVS protection device according to claim 1, wherein the semiconductor device comprises a first silicon-controlled rectifier SCR, wherein the first SCR comprises a first transistor (Q1_f) and a second transistor (Q2_f); wherein the first transistor has an emitter that is connected to the input terminal, wherein the first transistor has a collector that is in a same semiconductor region as a base of the second transistor, and wherein the first transistor has a base that is connected to a collector of the second transistor and to the IC terminal; wherein the second transistor has a collector that is connected to the base of the first transistor and to the IC terminal, wherein the second transistor has an emitter that is connected to the ground terminal, and wherein the second transistor has a base that is connected to the emitter of the first transistor.
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Claim 3 is objected to because of the following informalities: Claim 3 recites the limitation “fourth transistor (Q2_f)” in lines 3-4 of the claim. This appears to mean “fourth transistor (Q2_r)” based on Q2_f already being designated as the second transistor in claim 2 upon which claim 3 depends and the drawings filed 02/26/2025. Furthermore, the emitter and collector of the PNP transistor (i.e. fourth transistor (Q2_r) is referred to incorrectly. The collector of the PNP transistor is referred to as the emitter and the emitter is referred to as the collector. Based on the drawings filed 02/26/2025, the emitter of the fourth transistor is connected to the ground and the collector of the fourth transistor is connected to the base of the third transistor (refer to the drawing above and Wikipedia “Bipolar junction transistor”). Furthermore, Claim 3 recites the limitation “wherein the fourth transistor has a base that is connected to the collector of the first transistor”. As discussed above, the fourth transistor is Q2_r, the base of Q2_r is not connected to the collector of the first transistor. The base of the fourth transistor Q2_r is connected to the collector of the third transistor; however, claim 3 already recites that the collector of the third transistor is connected to the base of the fourth transistor (refer to claim 3 lines 7-8). Appropriate correction is required.
For the purposes of examination, Claim 3 is interpreted to recite: The TVS protection device according to claim 1, wherein the semiconductor device comprises a second SCR, wherein the second SCR comprises a third transistor (Q1_r) and a fourth transistor (Q2_r), wherein the third transistor has an emitter that is connected to the input terminal, wherein the third transistor has a collector that is connected to a base of the fourth transistor, and wherein the third transistor has a base that is connected to a collector of the fourth transistor and to the IC terminal, and wherein the fourth transistor has a collector that is connected to the base of the first transistor and to the IC terminal, and wherein the fourth transistor has an emitter that is connected to the ground terminal.
Claim 6 is objected to because of the following informalities: The emitter and collector of the PNP transistor (i.e. fifth transistor (Q1_f)) are referred to incorrectly. The collector of the PNP transistor is referred to as the emitter and the emitter is referred to as the collector. Based on the drawings filed 02/26/2025, the emitter of the fifth transistor is connected to the input terminal and the collector of the fifth transistor is connected to the ground (refer to Wikipedia “Bipolar junction transistor”). Furthermore, claim 6 recites the limitation “open base transistor” in lines 2 and 3. An open base transistor is a transistor with nothing connected to the base; however, the claim recites connections to the base of the open base transistor. This transistors is, therefore, not an open base transistor. Appropriate correction is required.For the purposes of examination, Claim 6 is interpreted to recite: The TVS protection device according to claim 1, wherein the semiconductor device comprises a first an emitter that is connected to the input terminal, wherein the fifth transistor has a collector that is connected to the ground terminal, and wherein the fifth transistor has a base that is connected to the IC terminal.
Claims 7-9, 19, and 20 are objected to because of the following informalities: The claims recite the limitation “open base transistor” or “open transistor” in multiple places. An open base transistor is a transistor with nothing connected to the base; however, the claims recite connections to the base of the open base transistors. These transistors are, therefore, not open base transistors. For the purposes of examination, all instances of “open base transistor” or “open transistor” will be interpreted as “transistor”. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: Claim 19 recites “The TVS protection device according to claim 1, wherein the first open base transistor includes a bipolar junction transistor (BJT).” To overcome an antecedent basis issue, this appears to mean: “The TVS protection device according to claim[[ 1]] 6, wherein the first open base transistor includes a bipolar junction transistor (BJT).” Appropriate correction is required.
Claim 20 is objected to because of the following informalities: Claim 20 recites “The TVS protection device according to claim 6, wherein the second open base transistor includes a bipolar junction transistor (BJT).” To overcome an antecedent basis issue, this appears to mean: “The TVS protection device according to claim[[ 6]] 7, wherein the second open base transistor includes a bipolar junction transistor (BJT).” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Talliet U.S. Patent No. 5,903,424 (hereinafter “Talliet”).
Regarding claim 1, Talliet teaches a transient voltage suppressor (TVS) protection device (refer to abstract and figure 1) comprising: an input terminal (i.e. pad PL)(fig.1); an integrated circuit (IC) terminal (i.e. node E)(fig.1); a ground terminal (i.e. VSS)(fig.1); a resistor (i.e. resistor R1)(fig.1) connected between the input terminal and the IC terminal (implicit)(refer to fig.1); and a semiconductor device (i.e. transistors T1 and T2)(fig.1) arranged to be triggered by a voltage drop across the resistor to open a path between the input terminal and the ground terminal (implicit)(refer to abstract and figure 1).
Regarding claim 2, Talliet teaches the TVS protection device according to claim 1, wherein the semiconductor device comprises a first silicon-controlled rectifier SCR (refer to transistors T1 and T2)(fig.1), wherein the first SCR comprises a first transistor (Q1_f) (i.e. PNP transistor T1)(fig.1) and a second transistor(Q2_f) (i.e. NPN transistor T2)(fig.1); wherein the first transistor has an emitter that is connected to the input terminal (implicit)(refer to fig.1),wherein the first transistor has a collector that is in a same semiconductor region as a base of the second transistor (implicit)(refer to 10)(figs.1 and 2), and wherein the first transistor has a base that is connected to a collector of the second transistor (implicit)(refer to fig.1) and to the IC terminal (implicit)(refer to fig.1); wherein the second transistor has a collector that is connected to the base of the first transistor and to the IC terminal (implicit)(refer to fig.1), wherein the second transistor has an emitter that is connected to the ground terminal (implicit)(refer to fig.1), and wherein the second transistor has a base that is connected to the emitter of the first transistor (implicit)(refer to fig.1).
Regarding claim 4, Talliet teaches the TVS protection device according to claim 2, wherein the TVS protection device is a unidirectional SCR based protection device (implicit)(refer to fig.1).
Claim(s) 1, 6, 8, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yasuda et al. Japanese Patent Document JP S59-61169 A (hereinafter “Yasuda”).
Regarding claim 1, Yasuda teaches a transient voltage suppressor (TVS) protection device (refer to abstract and figure 3) comprising: an input terminal (i.e. input terminal 1)(fig.3); an integrated circuit (IC) terminal (refer to internal circuit 4)(fig.3); a ground terminal (implicit)(refer to fig.3); a resistor (i.e. resistor 13)(fig.3) connected between the input terminal and the IC terminal (implicit)(refer to fig.3); and a semiconductor device (i.e. transistor 12)(fig.3) arranged to be triggered by a voltage drop across the resistor to open a path between the input terminal and the ground terminal (implicit)(refer to abstract and figure 3).
Regarding claim 6, Yasuda teaches the TVS protection device according to claim 1, wherein the semiconductor device comprises a first transistor (i.e. transistor 12)(fig.3), wherein the first open base transistor comprises a fifth transistor (Q1_f) (i.e. transistor 12)(fig.3), and wherein the fifth transistor has an emitter that is connected to the input terminal (i.e. E)(fig.3), wherein the fifth transistor has a collector that is connected to the ground terminal (i.e. C)(fig.3), and wherein the fifth transistor has a base that is connected to the IC terminal (i.e. B)(fig.3).
Regarding claim 8, Yasuda teaches the TVS protection device according to claim 6, wherein the TVS protection device is a unidirectional open transistor based protection device (implicit)(refer to fig.3).
Regarding claim 19, Yasuda teaches the TVS protection device according to claim 6, wherein the first open base transistor includes a bipolar junction transistor (BJT) (refer to transistor 12)(fig.3.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 5, and 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talliet as applied to claim 1 above, and further in view of Hung Canadian Patent Document CA 1330451 C (hereinafter “Hung”).
Regarding claim 3, Talliet teaches the TVS protection device according to claim 2; however, Talliet does not teach wherein the semiconductor device comprises a second SCR, wherein the second SCR comprises a third transistor (Q1_r) and a fourth transistor (Q2_r), wherein the third transistor has an emitter that is connected to the input terminal, wherein the third transistor has a collector that is connected to a base of the fourth transistor, and wherein the third transistor has a base that is connected to a collector of the fourth transistor and to the IC terminal, and wherein the fourth transistor has a collector that is connected to the base of the first transistor and to the IC terminal, and wherein the fourth transistor has an emitter that is connected to the ground terminal. However, Hung teaches wherein the semiconductor device comprises a second SCR (refer to transistors Q1 and Q2)(fig.5), wherein the second SCR comprises a third transistor (Q1_r) (i.e. NPN transistor Q1)(fig.5) and a fourth transistor (Q2_r) (i.e. PNP transistor Q2)(fig.5), wherein the third transistor has an emitter that is connected to the input terminal (implicit)(refer to contact 112)(fig.5), wherein the third transistor has a collector that is connected to a base of the fourth transistor (implicit)(refer to fig.5), and wherein the third transistor has a base that is connected to a collector of the fourth transistor and to the IC terminal (implicit)(refer to contact 114)(fig.5), and wherein the fourth transistor has a collector that is connected to the base of the first transistor (refer to transistor Q3)(fig.5) and to the IC terminal (implicit)(refer to contact 114)(fig.5), and wherein the fourth transistor has an emitter that is connected to the ground terminal (implicit)(refer to contact 116)(fig.5).
Regarding claim 5, Talliet and Hung teach the TVS protection device according to claim 3, wherein the TVS protection device is a bidirectional SCR based protection device (implicit)(refer to Hung fig.5).
Regarding claim 13, Talliet teaches the TVS protection device according to claim 1; however, Talliet does not teach wherein the resistor is an external resistor formed by a second semiconductor region in between the input connector and the IC connector, and wherein the second semiconductor region is independent from the semiconductor device. However, Hung teaches wherein the resistor is an external resistor (i.e. resistor 12)(fig.5) formed in between the input connector and the IC connector (implicit)(refer to Hung contacts 112 and 114)(fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the external resistor of Hung to provide the advantage of using common type of resistor for a semiconductor device. However, Talliet and Hung do not teach the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device. However, it would have been an obvious matter of design choice to have the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device, since applicant has not disclosed that having the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with any type of resistor. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet and Hung to include the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device to provide the advantage of using a common type of resistor for a semiconductor device.
Regarding claim 14, Talliet teaches the TVS protection device according to claim 1; however, Talliet does not teach wherein the resistor is an external resistor in between the input connector and the IC connector, and wherein the resistor is located outside of a semiconductor package of the TVS protection device. However, Hung teaches wherein the resistor is an external resistor (i.e. resistor 12)(fig.2) in between the input connector and the IC connector (implicit)(refer to contacts 112 and 114)(fig.5), and wherein the resistor is located outside of a semiconductor package of the TVS protection device (implicit)(refer to protection module 100)(fig.5)(refer also to page 10 lines 21-23). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the external resistor of Hung to provide the advantage of using a common type of resistor for a semiconductor device.
Regarding claim 15, Talliet teaches a TVS protection device according to claim 1, however, Talliet does not teach a semiconductor package comprising the TVS protection device, the semiconductor package comprising at least three externally accessible connection points connecting to an input terminal, an integrated circuit (IC) terminal and a ground terminal, respectively, of the TVS protection device. However, Hung teaches a semiconductor package (refer to protection module 100)(fig.5)(refer also to page 10 lines 21-23) comprising the TVS protection device (implicit), the semiconductor package comprising at least three externally accessible connection points (refer to contacts 112, 114, and 116)(fig.5) connecting to an input terminal (i.e. tip line 32)(fig.5), an integrated circuit (IC) terminal (i.e. ring line 22)(fig.5) and a ground terminal (implicit), respectively, of the TVS protection device (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the TVS protection device of Talliet to include the package and external connection points of Hung to provide the advantage of protecting the device while allowing easy connection to the device.
Regarding claim 16, Talliet teaches the TVS protection device according to claim 2; however, Talliet does not teach wherein the resistor is an external resistor formed by a second semiconductor region in between the input connector and the IC connector, and wherein the second semiconductor region is independent from the semiconductor device. However, Hung teaches wherein the resistor is an external resistor (i.e. resistor 12)(fig.5) formed in between the input connector and the IC connector (implicit)(refer to Hung contacts 112 and 114)(fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the external resistor of Hung to provide the advantage of using common type of resistor for a semiconductor device. However, Talliet and Hung do not teach the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device. However, it would have been an obvious matter of design choice to have the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device, since applicant has not disclosed that having the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with any type of resistor. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet and Hung to include the resistor formed by a second semiconductor region and wherein the second semiconductor region is independent from the semiconductor device to provide the advantage of using a common type of resistor for a semiconductor device.
Regarding claim 17, Talliet teaches the TVS protection device according to claim 2; however, Talliet does not teach wherein the resistor is an external resistor in between the input connector and the IC connector, and wherein the resistor is located outside of a semiconductor package of the TVS protection device. However, Hung teaches wherein the resistor is an external resistor (i.e. resistor 12)(fig.2) in between the input connector and the IC connector (implicit)(refer to contacts 112 and 114)(fig.5), and wherein the resistor is located outside of a semiconductor package of the TVS protection device (implicit)(refer to protection module 100)(fig.5)(refer also to page 10 lines 21-23). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the external resistor of Hung to provide the advantage of using a common type of resistor for a semiconductor device.
Regarding claim 18, Talliet teaches a TVS protection device according to claim 2, however, Talliet does not teach a semiconductor package comprising the TVS protection device, the semiconductor package comprising at least three externally accessible connection points connecting to an input terminal, an integrated circuit (IC) terminal and a ground terminal, respectively, of the TVS protection device. However, Hung teaches a semiconductor package (refer to protection module 100)(fig.5)(refer also to page 10 lines 21-23) comprising the TVS protection device (implicit), the semiconductor package comprising at least three externally accessible connection points (refer to contacts 112, 114, and 116)(fig.5) connecting to an input terminal (i.e. tip line 32)(fig.5), an integrated circuit (IC) terminal (i.e. ring line 22)(fig.5) and a ground terminal (implicit), respectively, of the TVS protection device (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the TVS protection device of Talliet to include the package and external connection points of Hung to provide the advantage of protecting the device while allowing easy connection to the device.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talliet as applied to claim 2 above, and further in view of Wada Japanese Patent Document JP 2009-71261 A (hereinafter “Wada”).
Regarding claim 10, Talliet teaches the TVS protection device according to claim 2; however, Talliet does not teach the device further comprising: a first diode, wherein the first diode has a cathode that is connected to the input terminal, and wherein the first diode has an anode that is connected to the ground terminal. However, Wada teaches the device further comprising: a first diode (i.e. diode 15)(fig.1), wherein the first diode has a cathode that is connected to the input terminal (implicit)(refer to input terminal 16)(fig.1), and wherein the first diode has an anode that is connected to the ground terminal (implicit)(refer to ground terminal 17)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the diode of Wada to provide the advantage of further protecting the IC from damage due to ESD.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Talliet as applied to claim 1 above, and further in view of Czech et al. U.S. Patent Application 2001/0019138 (hereinafter “Czech”).
Regarding claim 12, Talliet teaches the TVS protection device according to claim 1, wherein the resistor is an internal resistor (i.e. resistor R1)(fig.1)(refer also to col. 5 line 66 to col. 6 line 3) formed by a region in between the input connector and the IC connector (implicit)(refer to figs.1 and 2)(refer also to col. 5 line 66 to col. 3 line 3); however, Talliet does not teach the region being a first semiconductor region, and wherein the first semiconductor region is a part of the semiconductor device. However, Czech teaches the region being a first semiconductor (refer to [0043]), and wherein the first semiconductor region is a part of the semiconductor device (refer to [0043]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Talliet to include the semiconductor resistor of Czech to provide the advantage of using a common type of resistor for a semiconductor device.
Allowable Subject Matter
Claims 7, 9, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and to overcome the above objections.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 11 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 11, especially The TVS protection device according to claim 3, further comprising: a second diode, wherein the second diode has an anode that is connected to the input terminal, and wherein the second diode has a cathode that is connected to the ground terminal.
Claims 7, 9, and 20 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 7, especially wherein the semiconductor device comprises a second open base transistor, wherein the second open base transistor comprises a sixth transistor (Q1_r), and wherein the sixth transistor has a collector that is connected to the input terminal, wherein the sixth transistor has an emitter that is connected to the ground terminal, and wherein the sixth transistor has a base that is connected to the IC terminal. Claims 9 and 20 are indicated as containing allowable subject matter based on their dependency on claim 7.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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