DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-11 and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 2023/0049678) and further in view of “Counting Bloom Filters: A Gentle Introduction”, henceforth referred to as Oparin.
Consider claim 1, Palmer discloses a memory device, comprising: one or more components configured to: receive, from a host system, a first access request indicating that a portion of a memory is to be accessed by the memory device; identify a first-level block of memory, of multiple first-level blocks of memory, that is associated with the portion of the memory; identify that a first access counter associated with the first-level block of memory satisfies a first-level access threshold; identify a second-level block of memory, of multiple second-level blocks of memory, that is associated with the portion of the memory based on identifying that the first access counter satisfies the first-level access threshold; identify that a second access counter associated with the second-level block of memory satisfies a second-level access threshold (abstract, [0011], [0012], [0039], [0040], [0069], [0075], Palmer discloses a system where reads are received from a host and passed through multiple layers of portions of memory with associated counters tracking the amount of reads to that portion of memory. If a portion of memory meets a threshold condition, the granularity of that portion of memory can be reduced and split up. These new portions of memory have counters associated with them. Counters are incremented upon a read request to a portion of memory associated with the counter.); identify a third-level block of memory, of multiple third-level blocks of memory, associated with the portion of the memory based on identifying that the second access counter satisfies the second-level access threshold; and increment a third access counter associated with the third-level block of memory (abstract, [0011], [0012], [0039], [0040], [0069], [0075], Palmer discloses that the process described directly above can go on for another layer reducing granularity.).
As for the limitation: the third access counter being implemented using a counting bloom filter. Palmer does not explicitly disclose that the access counter of the third level can be a counting bloom filter. However, Oparin discloses the use of a counting bloom filter (Headings: “What is a Counting Bloom Filter” and “Advantages and Limitations”.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify any access counter of Palmer, including the third access counter to be a counting bloom filter because counting bloom filters are space efficient counting structures (Headings: “What is a Counting Bloom Filter”).
Consider claim 2, Palmer discloses the memory device of claim 1, wherein the one or more components are further configured to: receive, from the host system, a second access request indicating that the portion of the memory is to be accessed by the memory device; identify that the second access counter associated with the second-level block of memory satisfies the second-level access threshold; (abstract, [0011], [0012], [0039], [0040], [0069], [0075], Palmer discloses that the process described in claim 1 above can go on for another layer reducing granularity.).
Consider claim 3, Palmer discloses the memory device of claim 2, wherein at least one of the first access counter and the second access counter is associated with a hardware-based access counter (Palmer: abstract, [0011], [0012], [0039], [0040], [0069], [0075], discloses counters and these counters are based in hardware.).
Consider claim 5, Palmer discloses the memory device of claim 1, where a size of the first-level block of memory is larger than a size of the second-level block of memory (abstract, [0011], [0012], [0039], [0040], [0069], [0075], Palmer discloses that the first level portion of memory is the largest and gets smaller with each granularity change.).
Consider claim 6, Palmer discloses the memory device of claim 1, wherein the one or more components are further configured to add an identifier of the first-level block of memory to a first-level data structure based on identifying that the first access counter satisfies the first-level access threshold (abstract, [0011], [0012], [0039], [0040], [0069], [0070], [0075], [0077], Palmer discloses using a tree structure and adding new entries as counter thresholds are met. Further the granularity of memory is tracked.).
Consider claim 7, Palmer discloses the memory device of claim 6, wherein the one or more components are further configured to: receive, from the host system, a second access request indicating that the portion of the memory is to be accessed by the memory device; identify that the second access counter associated with the second-level block of memory satisfies the second-level access threshold; and add an identifier of the second-level block of memory to a second-level data structure based on identifying that the second access counter satisfies the second-level access threshold (abstract, [0011], [0012], [0039], [0040], [0069], [0070], [0075], [0077], Palmer discloses using a tree structure and adding new entries as counter thresholds are met. Further the granularity of memory is tracked. Palmer discloses a system where reads are received from a host and passed through multiple layers of portions of memory with associated counters tracking the amount of reads to that portion of memory. If a portion of memory meets a threshold condition, the granularity of that portion of memory can be reduced and split up. These new portions of memory have counters associated with them.).
Consider claim 8, Palmer discloses the memory device of claim 1, wherein the one or more components are further configured to: identify that a monitoring period has elapsed; and reduce a value of the first access counter and a value of the second access counter based on identifying that the monitoring period has elapsed ([0066], Palmer discloses having a monitoring period and reducing/resetting counters.).
Claims 9-11 and 13-16 are the method claims to device claims 1-3 and 5-8 above and are rejected in the same manner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 2023/0049678) and further in view of “Lightweight Frequency-based Tiering for CXL Memory Systems”, henceforth referred to as Song et al. and “Counting Bloom Filters: A Gentle Introduction”, henceforth referred to as Oparin.
Consider claim 17, Palmer in view of Song et al. discloses a compute express link (CXL) compliant memory device, comprising: one or more components configured to: receive, from a host system, a first access request indicating that a portion of a memory is to be accessed by the CXL compliant memory device; identify a first-level block of memory, of multiple first-level blocks of memory, that is associated with the portion of the memory; increment a first hotness counter associated with the first-level block of memory; identify that the first hotness counter satisfies a first-level hotness threshold; add an identifier of the first-level block of memory to a first-level hotlist based on identifying that the first hotness counter satisfies the first-level hotness threshold; receive, from the host system, a second access request indicating that the portion of the memory is to be accessed by the CXL compliant memory device; identify a second-level block of memory, of multiple second-level blocks of memory, that is associated with the portion of the memory; increment a second hotness counter associated with the second-level block of memory; identify that the second hotness counter satisfies a second-level hotness threshold; add an identifier of the second-level block of memory to a second-level hotlist based on identifying that the second hotness counter satisfies the second- level hotness threshold; receive, from the host system, a third access request indicating that the portion of the memory is to be accessed by the CXL compliant memory device; identify a third-level block of memory, of multiple third-level blocks of memory; increment a third hotness counter associated with the third-level block of memory; identify that the third hotness counter satisfies a third-level hotness threshold; and add an identifier of the third-level block of memory to a third-level hotlist based on identifying that the third hotness counter satisfies the third-level hotness threshold (abstract, [0011], [0012], [0039], [0040], [0069], [0075], Palmer discloses a system where reads are received from a host and passed through multiple layers of portions of memory with associated counters tracking the amount of reads to that portion of memory. If a portion of memory meets a threshold condition, the granularity of that portion of memory can be reduced and split up. These new portions of memory have counters associated with them. Counters are incremented upon a read request to a portion of memory associated with the counter. Palmer discloses that this process can go on for another layer reducing granularity. Palmer discloses using a tree structure and adding new entries as counter thresholds are met. Further the granularity of memory is tracked. These new portions of memory have counters associated with them. Palmer does not disclose the use of CXL, however Song et al. does teach CXL compliant memory abstract, introduction: first two paragraphs.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the memory system of the Palmer reference to include CXL as in Song et al. because CXL memory tiering is an industry standard interconnect protocol that provides a high speed CPU to memory connection with coherency that allows memory resources to be pooled, shared and scaled efficiently and cost effectively (Song et al.: abstract, introduction: first two paragraphs.).
As for the limitation: the third hotness counter being implemented using a counting bloom filter. Palmer does not explicitly disclose that the hotness counter of the third level can be a counting bloom filter. However, Oparin discloses the use of a counting bloom filter (Headings: “What is a Counting Bloom Filter” and “Advantages and Limitations”.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify any hotness counter of Palmer, including the third access counter to be a counting bloom filter because counting bloom filters are space efficient counting structures (Headings: “What is a Counting Bloom Filter”).
Consider claim 18, Palmer in view of Song et al. discloses the CXL compliant memory device of claim 17, wherein at least one of the first hotness counter and the second hotness counter are associated with a hardware-based hotness counter (Palmer: abstract, [0011], [0012], [0039], [0040], [0069], [0075], discloses counters and these counters are based in hardware. Song et al. Fig. 4 and the accompanying sections of the reference.).
Consider claim 20, Palmer in view of Song et al. discloses the CXL compliant memory device of claim 17, wherein the one or more components are further configured to: identify that a hotness counting period has elapsed; and reduce a value of the first hotness counter, a value of the second hotness counter, and a value of the third hotness counter based on identifying that the hotness counting period has elapsed ([0066], Palmer discloses having a monitoring period and reducing/resetting counters.).
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 2023/0049678) in view of “Counting Bloom Filters: A Gentle Introduction”, henceforth referred to as Oparin as applied to claims 3 and 11 above, and further in view of KSR.
Consider claim 4, Palmer discloses having memory portion sizes that reduce with each granularity adjustment as described in the rejections of claims 1-3 and 5 above. Palmer also states that that tracking of memory portions can be as small as 4 kilobytes ([0038]). However, Palmer does not explicitly state that first level size is 1 gigabyte and second level size is 2 megabytes. However, the values of 1GB and 2MBs are well within the range of well-known values utilized in memory systems in general for grouping capacity and therefore the examiner is using the KSR rationale of “obvious to try” to reject this minor difference between the claim language and the Palmer reference.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Palmer reference to have the specific memory sizes claimed because these values are well within the range of well-known values utilized in memory systems in general for grouping capacity and choosing these values are choices made from a finite number of identifiable, predictable solutions with a reasonable expectation of success.
Claim 12 is the method claim to device claim 4 above and is rejected in the same manner.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 2023/0049678) in view of “Lightweight Frequency-based Tiering for CXL Memory Systems”, henceforth referred to as Song et al. and “Counting Bloom Filters: A Gentle Introduction”, henceforth referred to as Oparin as applied to claim 17 above, and further in view of KSR.
Consider claim 19, Palmer discloses having memory portion sizes that reduce with each granularity adjustment as described in the rejections of claims 17 above. Palmer also states that that tracking of memory portions can be as small as 4 kilobytes ([0038]). However, Palmer does not explicitly state that first level size is 1 gigabyte and second level size is 2 megabytes. However, the values of 1GB and 2MBs are well within the range of well-known values utilized in memory systems in general for grouping capacity and therefore the examiner is using the KSR rationale of “obvious to try” to reject this minor difference between the claim language and the Palmer reference.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Palmer reference to have the specific memory sizes claimed because these values are well within the range of well-known values utilized in memory systems in general for grouping capacity and choosing these values are choices made from a finite number of identifiable, predictable solutions with a reasonable expectation of success.
Response to Arguments
Applicant's arguments filed 7/31/2026 have been fully considered but they are not persuasive. The arguments pertain to the new claim limitations which have been addressed by the introduction of the Oparin reference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ALSIP/ Primary Examiner, Art Unit 2139
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