DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: comparison unit in claim 1 and 17-19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The specification discloses on page 35, lines 1-8: “In embodiments, the one or more graphics processing units may comprise two graphics processing units, and wherein each of the two graphics processing units may be configured to, during a single geometry processing pass: i) process all of the geometry data to generate the one or more primitives, and ii) generate a respective checksum based on the one or more primitives, and wherein a comparison unit is configured to compare the respective checksums, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.” The corresponding structure, for the comparison unit, is considered to be the one or more graphics processing units.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,265,450. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Instant Application is a broader version of the claims of the U.S. Patent.
Instant Application - 19/063,584
U.S. Patent No. 12,265,450
1. A graphics processing system for performing tile-based rendering of a scene, wherein the system comprises:
a plurality of graphics processing units, wherein each graphics processing unit is configured to i) receive tile data identifying one or more protected tiles, and ii) generate a checksum for a set of protected tiles, wherein the set of protected tiles is processed by two different graphics processing units;
and a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
1. A graphics processing system for performing tile-based rendering of a scene, wherein the system comprises:
a plurality of graphics processing units, wherein each graphics processing unit is configured to i) receive tile data identifying one or more protected tiles, ii) process two respective sets of the protected tiles, and iii) based on said processing, generate two respective checksums, one for each respective set of protected tiles, wherein each respective set of protected tiles is processed by two different graphics processing units;
and a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a respective checksum generated based on a same respective set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
Claim 1 of the Instant Application is a broader version of Claim 1 of the U.S. Patent.
2. The graphics processing system of claim 1, wherein the one or more actions comprise, if any of the pairs of checksums comprise non-matching checksums: raising a fault signal, and/or causing one or more protected tiles to be re-processed by one, some or each graphic processing unit.
2. The graphics processing system of claim 1, wherein the one or more actions comprise, if any of the pairs of checksums comprise non-matching checksums: raising a fault signal, and/or causing one or more protected tiles to be re-processed by one, some or each graphic processing unit.
3. The graphics processing system of claim 2, wherein the one or more protected tiles to be re-processed belong to a set of protected tiles upon which non-matching checksums are generated.
3. The graphics processing system of claim 2, wherein the one or more protected tiles to be re-processed belong to a set of protected tiles upon which non-matching checksums are generated.
4. The graphics processing system of claim 1, wherein each graphics processing unit is configured to:
during a first fragment processing pass, generate a checksum based on a first set of protected tiles;
and during a second fragment processing pass, generate a checksum based on a second set of protected tiles, wherein the second fragment processing pass begins after the first fragment processing pass has ended.
4. The graphics processing system of claim 1, wherein each graphics processing unit is configured to:
during a first fragment processing pass, process a first one of the two respective sets of protected tiles and generate the respective checksum generated based on the first set of protected tiles;
and during a second fragment processing pass, process a second one of the two respective sets of protected tiles and generate the respective checksum generated based on the second set of protected tiles, wherein the second fragment processing pass begins after the first fragment processing pass has ended.
5. The graphics processing system of claim 4, wherein each graphics processing unit is configured to: output pixel data generated based on the second set of protected tiles to one or more buffers during the second fragment processing pass but not during the first fragment processing pass.
9. The graphics processing system of claim 1, wherein each graphics processing unit is configured to: output pixel data generated based on the second set of protected tiles to one or more buffers during the second fragment processing pass but not during the first fragment processing pass.
6. The graphics processing system of claim 4, wherein each graphics processing unit is configured to: output pixel data generated based on the first set of protected tiles to one or more buffers during the first fragment processing pass but not during the second fragment processing pass.
5. The graphics processing system of claim 4, wherein each graphics processing unit is configured to: output pixel data generated based on the first set of protected tiles to one or more buffers during the first fragment processing pass but not during the second fragment processing pass.
7. The graphics processing system of claim 4, wherein at least one graphics processing unit is configured to: receive tile data identifying one or more non-protected tiles; and during the first and/or second fragment processing pass, output pixel data generated based on the one or more non-protected tiles to one or more buffers.
6. The graphics processing system of claim 4, wherein at least one graphics processing unit is configured to: during the first and/or second fragment processing pass, process one or more non-protected related tiles, and output pixel data generated based on the one or more non-protected tiles to one or more buffers.
8. The graphics processing system of claim 7, wherein each graphics processing unit is configured to: during the first and/or second fragment processing pass, output pixel data generated based on the one or more non-protected tiles to one or more buffers.
7. The graphics processing system of claim 6, wherein each graphics processing unit is configured to: during the first and/or second fragment processing pass, process one or more non-protected tiles, and output pixel data generated based on the one or more non-protected tiles to one or more buffers.
9. The graphics processing system of claim 1, wherein each graphics processing unit is configured to, during a single fragment processing pass: generate the checksum based on a first set of protected tiles;
and generate a checksum based on a second set of protected tiles.
10. The graphics processing system of claim 1, wherein each graphics processing unit is configured to, during a single fragment processing pass: process a first one of the two respective sets of protected tiles and generate the respective checksum based on the first set of protected tiles;
and process a second one of the two respective sets of protected tiles and generate the respective checksum based on the second set of protected tiles.
10. The graphics processing system of claim 9, wherein each graphics processing unit is configured to: output pixel data generated based on the first set of protected tiles to a pixel buffer but not pixel data generated based on the second set of protected tiles, wherein the respective pixel data generated based on each set of protected tiles is written to a pixel buffer by only one graphics processing unit.
11. The graphics processing system of claim 10, wherein each graphics processing unit is configured to: output pixel data generated based on the first set of protected tiles to a pixel buffer but not pixel data generated based on the second set of protected tiles, wherein the respective pixel data generated based on each set of protected tiles is written to a pixel buffer by only one graphics processing unit.
11. The graphics processing system of claim 9, wherein at least one graphics processing unit is configured to: receive tile data identifying one or more non-protected tiles; and output pixel data generated based on the one or more non-protected tiles to one or more buffers.
12. The graphics processing system of claim 10, wherein at least one graphics processing unit is configured to: process one or more non-protected related tiles, and output pixel data generated based on the one or more non-protected tiles to one or more buffers.
12. The graphics processing system of claim 9, wherein each protected tile is associated with a respective tile number and each graphics processing unit is associated with a respective graphics processing unit number,
wherein each protected tile is associated with a set identifier calculated as the respective tile number modulo a total number of the graphics processing units, and wherein, for each graphics processing unit, the first one of the two respective sets of protected tiles comprises one or more protected tiles having a respective set identifier corresponding to the respective graphics processing unit number,
and wherein for each graphics processing unit, the second one of the two respective sets of protected tiles comprises one or more protected tiles having a respective set identifier corresponding to the respective graphics processing unit number plus one, modulo the total number of the graphics processing units.
13. The graphics processing system of claim 10, wherein each protected tile is associated with a respective tile number and each graphics processing unit is associated with a respective graphics processing unit number,
wherein each protected tile is associated with a set identifier calculated as the respective tile number modulo a total number of the graphics processing units, and wherein, for each graphics processing unit, the first one of the two respective sets of protected tiles comprises one or more protected tiles having a respective set identifier corresponding to the respective graphics processing unit number,
and wherein for each graphics processing unit, the second one of the two respective sets of protected tiles comprises one or more protected tiles having a respective set identifier corresponding to the respective graphics processing unit number plus one, modulo the total number of the graphics processing units.
13. The graphics processing system of claim 7, wherein each non-protected tile is only processed once.
8. The graphics processing system of claim 6, wherein each non-protected tile is only processed once.
14. The graphics processing system of claim 1, wherein each graphics processing unit is configured to: generate or receive pixel data associated with the set of the protected tiles;
generate the checksum based on at least one of the following: a hash of the pixel data, a summation of the pixel data, a concatenation of the pixel data, a signature generated based on the pixel data, and an XOR operation applied to the pixel data.
14. The graphics processing system of claim 1, wherein each graphics processing unit is configured to: generate respective pixel data based on said processing of the two respective sets of the protected tiles;
and generate each respective checksum based on at least one of the following: a hash of the respective pixel data, a summation of the respective pixel data, a concatenation of the respective pixel data, a signature generated based on the respective pixel data, and an XOR operation applied to the respective pixel data.
15. The graphics processing system of claim 1, wherein the system comprises one or more graphics processing units configured to i) process input data relating to the scene to generate the one or more safety-related primitives, and ii) based on said processing of the input data, output the tile data identifying the one or more protected tiles.
15. The graphics processing system of claim 1, wherein the system comprises one or more graphics processing units configured to i) process input data relating to the scene to generate the one or more safety-related primitives, and ii) based on said processing of the input data, output the tile data identifying the one or more protected tiles.
16. The graphics processing system of claim 15, wherein the input data relating to the scene comprises geometry data describing elements in the scene, and wherein the one or more graphics processing units are configured to process the geometry data to produce the one or more primitives representing the elements from a point of view of a frame to be rendered.
16. The graphics processing system of claim 15, wherein the input data relating to the scene comprises geometry data describing elements in the scene, and wherein the one or more graphics processing units are configured to process the geometry data to produce the one or more primitives representing the elements from a point of view of a frame to be rendered.
17. The graphics processing system of claim 16, wherein the one or more graphics processing units consists of a single graphics processing units, and wherein the single graphics processing unit is configured to:
during a first geometry processing pass, process all of the geometry data to generate the one or more primitives and generate a first checksum based on the one or more primitives;
and during a second geometry processing pass, process all of the geometry data to generate the one or more primitives and generate a second checksum based on the one or more primitives;
wherein the second geometry processing pass begins after the first geometry processing pass has ended; wherein a comparison unit is configured to compare the first and second checksums, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
17. The graphics processing system of claim 16, wherein the one or more graphics processing units consists of a single graphics processing units, and wherein the single graphics processing unit is configured to:
during a first geometry processing pass, process all of the geometry data to generate the one or more primitives and generate a first checksum based on the one or more primitives;
and during a second geometry processing pass, process all of the geometry data to generate the one or more primitives and generate a second checksum based on the one or more primitives;
wherein the second geometry processing pass begins after the first geometry processing pass has ended, and wherein a comparison unit is configured to compare the first and second checksums, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
18. The graphics processing system of claim 16, wherein the one or more graphics processing units comprises two graphics processing units, and wherein each of the two graphics processing units is configured to, during a single geometry processing pass: i) process all of the geometry data to generate the one or more primitives, and ii) generate a checksum based on the one or more primitives;
wherein a comparison unit is configured to compare the checksums, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
18. The graphics processing system of claim 16, wherein the one or more graphics processing units comprises two graphics processing units, and wherein each of the two graphics processing units is configured to, during a single geometry processing pass: i) process all of the geometry data to generate the one or more primitives, and ii) generate a respective checksum based on the one or more primitives,
and wherein a comparison unit is configured to compare the respective checksums, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
19. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing system for performing tile-based rendering of a scene that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing system, wherein the graphics processing system comprises:
a plurality of graphics processing units, wherein each graphics processing unit is configured to i) receive tile data identifying one or more protected tiles, and ii) generate a checksum, for a set of protected tiles, wherein the set of protected tiles is processed by two different graphics processing units;
and a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a graphics processing system for performing tile-based rendering of a scene that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing system, wherein the graphics processing system comprises:
a plurality of graphics processing units, wherein each graphics processing unit is configured to i) receive tile data identifying one or more protected tiles, ii) process two respective sets of the protected tiles, and iii) based on said processing, generate two respective checksums, one for each respective set of protected tiles, wherein each respective set of protected tiles is processed by two different graphics processing units;
and a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a respective checksum generated based on a same respective set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
Claim 19 of the Instant Application is a broader version of Claim 19 of the U.S. Patent.
20. A method of performing tile-based rendering of a scene, the method comprising:
receiving by each of a plurality of graphics processing units tile data identifying one or more protected tiles, and generating a checksum for a set of protected tiles,
wherein the set of protected tiles is processed by two different graphics processing units;
comparing one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by a different graphics processing units; and performing one or more actions based on an outcome of said comparison.
20. A method of performing tile-based rendering of a scene, wherein the method comprises:
each of a plurality of graphics processing units receiving tile data identifying one or more protected tiles, processing two respective sets of the protected tiles, and based on said processing, generating two respective checksums, one for each respective set of protected tiles,
wherein each set of protected tiles is processed by two different graphics processing units;
comparing one or more pairs of checksums, wherein each pair comprises a respective checksum generated based on a same respective set of protected tiles and generated by a different graphics processing units; and performing one or more actions based on an outcome of said comparison.
Claim 20 of the Instant Application is a broader version of Claim 20 of the U.S. Patent.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the Nonstatutory Double Patenting Rejection, set forth in this Office Action.
The following is a statement of reasons for the indication of allowable subject matter: References King et al. U.S. Pub. No. 2020/0175645, Jong et al. U.S. Pub. No. 2019/0196926 and Gyllensward EP 2735 962 A1 made of record as teaching the art of tile region protection using multiple GPUs. However, none of the prior art teaches or suggests:
From claim 1 – “and a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.” Claims 2-18 depend directly or indirectly from claim 1 and include all of the limitations of claim 1.
From claim 19 – “a comparison unit configured to compare one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by different graphics processing units, and wherein the graphics processing system is configured to perform one or more actions based on an outcome of said comparison.”
From claim 20 – “comparing one or more pairs of checksums, wherein each pair comprises a checksum generated based on a same set of protected tiles and generated by a different graphics processing units; and performing one or more actions based on an outcome of said comparison.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. King et al. U.S. Pub. No. 2020/0175645, Jong et al. U.S. Pub. No. 2019/0196926 and Gyllensward EP 2735 962 A1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONNA J RICKS whose telephone number is (571)270-7532. The examiner can normally be reached on M-F 7:30am-5pm EST (alternate Fridays off).
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618
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