DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an application filed on February 26, 2025 and a Reply to Election of Species Requirement filed on May 7, 2026 regarding Application No. 19/063,675. Claims 4-5 and 15 are withdrawn as being directed to non-elected species. Claims 1-20 are pending.
Election/Restrictions
Claims 4-5 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a non-elected species, there being no allowable generic or linking claim.
Applicants timely traversed the restriction (election) requirement in the reply filed on May 7, 2026. In response to the arguments regarding the election of species requirement (Remarks, p. 6), the Office respectfully disagrees as the species include mutually exclusive characteristics, there is a search and/or an examination burden, and the pending claims are rejected, as discussed in the March 13, 2026 Office action and below, and the election of species requirement is maintained.
Priority
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the CN 202410334368.5 application filed in China on March 22, 2024 has been filed.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on February 26, 2025 and April 21, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Office. Please note that the Office has included the application number and/or art unit number on the IDSes.
Claim Objections
Claims 3, 11, and 18 are objected to for the reasons discussed below.
Claim 3: “(0.3 times the width of the first gate)” and “(0.7 times the width of the first gate)” should be changed to “[[(]]0.3 times the width of the first gate[[)]]” and “[[(]]0.7 times the width of the first gate[[)]]” since language within parenthesis are not part of the claim.
Claim 11: “a fourth transistor” (last line) should be changed to “[[a]]the fourth transistor” since the term was previously recited.
Claim 18: “a shspe of the second gate” should be changed to “[[a shspe]]the shape of the second gate” since the term was previously recited and to correct a typographical error.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features of claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. in US 2021/0216743 A1 (hereinafter Liu) in view of Kawase in US 2004/0235227 A1 (hereinafter Kawase).
Regarding claim 1, Liu teaches:
An electronic device (10 in FIG. 1), comprising (Liu: FIG. 1 and “[0030] FIG. 1 is a functional block diagram of an electronic device 10....”, see also FIGs. 2-3 and 13):
a substrate (100 in FIG. 1) (Liu: FIG. 1 and “[0030]... The electronic device 10 includes a substrate 100....”);
a first conductive layer (601 in FIGs. 6 and 8) disposed on the substrate and provided with a first gate (600(G1) in FIG. 8) and a line segment (601(SC[1] in FIG. 5), wherein the line segment is connected to the first gate (Liu: FIGs. 2-8, [0039] (row selecting signals SC[1] in FIG. 2), “[0053]... [T]he transistor M1 may... include the conductive layer 600, has a double gate structure, and includes a control terminal G1 and a control terminal G2.... [T]he double gate structure may be, for example, different conductive layers (e.g., the conductive layers 600, 601) located in opposite upper and lower sides of the same semiconductor layer to control the corresponding semiconductor layer....”, and “[0056] The conductive layer 601 receives the row selecting signal SC[1]....”);
an electronic unit (e.g., OLED) and a sensor unit (D11 in FIG. 4) respectively disposed on the substrate (Liu: FIGs. 1 and 4, “[0030]... The pixel unit[] PX11... [of the non-peripheral area 101 of the substrate 100]... can be, for example, organic light emitting diode (OLED)....”, “[0032]... [T]he sensing unit[] PD11... in the non-peripheral area 101 [of the substrate 100]....”, and “[0044].... The sensing unit PD11 includes... a sensing photodiode D11....”, see also FIG. 17 (electronic unit OD11 and sensor unit D11)); and
a sensor unit driving circuit (PD11 in FIG. 4) disposed on the substrate and electrically connected to the electronic unit and the sensor unit (Liu: FIGs. 2 and 4 and “[0031]... [A] sensing unit PD11 [of integration unit U11 in the non-peripheral area 101 of the substrate 100], are integrated within the integration unit U11....”, see also FIG. 17),
wherein the sensor unit driving circuit includes a first transistor (M1 in FIGs. 4 and 8), the first transistor has the first gate (Liu: FIGs. 4 and 8, “[0044]... The sensing unit PD11 includes... a transistor M1....”, and “[0053]... [T]he transistor M1 may... include the conductive layer 600, has a double gate structure, and includes a control terminal G1 and a control terminal G2....”).
However, it is noted that Liu does not teach:
a shape of the first gate is different from a shape of the line segment.
Kawase teaches:
a shape of a first gate (31 in Fig. 7) is different from a shape of a line segment (30) (Kawase: Fig. 7 and “[0105]... The gate line 30 is provided with a region which is of increased width in comparison to the gate line 30 and which functions as a gate electrode 31....”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Kawase, such that Liu as modified teaches: wherein the sensor unit driving circuit includes a first transistor, the first transistor has the first gate, and a shape of the first gate is different from a shape of the line segment (sensor unit driving circuit, first transistor, first gate, and line segment of Liu combined with the shape of a first gate and shape of a line segment of Kawase), to provide a thin film transistor. (Kawase: “[0001] The present invention relates to a circuit fabrication method, and in particular to a fabrication method for thin film transistor circuits.”).
Regarding claim 2, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 1, wherein the shape of the first gate being different from the shape of the line segment indicates that a width of the first gate is different from a width of the line segment (Kawase: Fig. 7 and “[0105]... The gate line 30 is provided with a region which is of increased width in comparison to the gate line 30 and which functions as a gate electrode 31....”).
Regarding claim 3, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 2, wherein a ratio of the width of the line segment to the width of the first gate satisfies an equation: (0.3 times the width of the first gate) < the ratio < (0.7 times the width of the first gate) (It would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for channel width optimization. Kawase: see Figs. 9-11 and [0109]-[0113]).
Regarding claim 6, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 1, further comprising a second conductive layer (600 in FIG. 6 of Liu) disposed on the first conductive layer, wherein the second conductive layer includes a second gate (600(G2) in FIG. 8 of Liu), the first transistor has the second gate, and the second gate of the first transistor at least partially overlaps the first gate of the first transistor (Liu: FIGs. 6 and 8 and “[0053]... [T]he transistor M1... has a double gate structure, and includes a control terminal G1 and a control terminal G2.... [T]he double gate structure may be, for example, different conductive layers (e.g., the conductive layers 600, 601) located in opposite upper and lower sides of the same semiconductor layer to control the corresponding semiconductor layer....”).
Regarding claim 7, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 6, wherein a shape of the first gate is different from a shape of the second gate (Liu: see FIG. 8).
Regarding claim 8, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 7, wherein the shape of the first gate being different from the shape of the second gate indicates that a width of the first gate is different from a width of the second gate (Liu: see FIG. 8).
Regarding claim 9, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 1, further comprising an electronic unit driving circuit (PX11 in FIGs. 1 and 4 of Liu) disposed on the substrate, wherein the first conductive layer includes a second gate (601/control terminal of M5 in FIG. 6), the electronic unit driving circuit includes a second transistor (M5 in FIG. 4), the second transistor has the second gate, and a shape of the second gate is different from the shape of the line segment (Liu: electronic unit driving circuit, first conductive layer, and second transistor as claimed; see FIGs. 1, 4, and 6, “[0030]... [T]he non-peripheral area 101 [of the substrate 100] includes pixel unit[] PX11....”, “[0046] The pixel unit PX11 is corresponding to the transistor M5....”, “[0047]... The transistor M5 includes a control terminal....”, and “[0050] In FIG. 6,... the conductive layer 601 is disposed on the insulating layer 612 [disposed on layers disposed on the substrate 100]....”, see also FIG. 8; Kawase: a shape of a second gate 31 is different from a shape of a line segment 30; Fig. 7 and “[0105]... The gate line 30 is provided with a region which is of increased width in comparison to the gate line 30 and which functions as a gate electrode 31....”).
Regarding claim 12, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 9, wherein the line segment is connected to the second gate (Liu: FIGs. 4-6 and “[0047]... The transistor M5 includes a control terminal....”, see also FIG. 8).
Claims 10-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Kawase, in further view of Lius et al. in US 2020/0312936 A1 (hereinafter Lius).
Regarding claim 10, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 9, wherein the electronic device further includes an active area (101 in FIG. 2 of Liu) and a peripheral area (102), the peripheral area is adjacent to the active area, the sensor unit driving circuit and the electronic unit driving circuit are disposed in the active area (Liu: FIGs. 2 and 4, “[0030]... The substrate 100 [of the electronic device 10] includes a non-peripheral area 101 and a peripheral area 102, wherein the non-peripheral area 101 includes pixel unit[] PX11....”, and “[0031] There... [is an] integration unit[] U11... in the non-peripheral area 101 [of the substrate 100].... [C]omponents for sensing and display, including the pixel PX11... and a sensing unit PD11... are integrated within the integration unit U11....”).
However, it is noted that Liu as modified by Kawase does not teach:
further comprising a third transistor disposed on the substrate, the third transistor is disposed in the peripheral area, and the third transistor controls a signal to the first transistor and the second transistor.
Lius teaches:
a third transistor (of 120, or 122, in FIG. 4) disposed on a substrate (14), the third transistor is disposed in a peripheral area (12), and the third transistor controls a signal to a transistor (of Pd(1,1), or Ps(1,1)) (Lius: FIGs. 1 and 4, [0024] (including: “... The display device 1 [in FIG. 1] has a display region 10 and a side region 12 adjacent to the display region 10....”), “[0025] (including: “.... The display gate driver 120 may be coupled to a portion of the plurality of display units 100 and may comprise a plurality of first thin-film transistors to select display units 100 via corresponding display driving units 102.... Similarly, the sensor gate driver 122 may be coupled to a portion of the plurality of sensing units 104 and may comprise a plurality of second thin-film transistors to select sensing units 104 via corresponding sensor driving units 106.... At least a portion of the plurality of first thin-film transistors and at least a portion of the plurality of second thin-film transistors are disposed in the side region 12.”), “[0027]... FIG. 2 shows that the display device 1 further comprises an array substrate 14....”, and “[0030]... [T]he display gate driver 120 and the sensor gate driver 122 [in FIG. 4] share the side region 12....”, see also FIG. 5, FIG. 9 (third transistor M3, or M4), FIG. 10, [0031]-[0032], and [0036]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Lius, such that Liu as modified teaches:
further comprising a third transistor disposed on the substrate, wherein the electronic device further includes an active area and a peripheral area, the peripheral area is adjacent to the active area, the sensor unit driving circuit and the electronic unit driving circuit are disposed in the active area, the third transistor is disposed in the peripheral area, and the third transistor controls a signal to the first transistor and the second transistor (substrate, electronic device, active and peripheral areas, and sensor and electronic unit driving circuits of Liu as modified combined with the third transistor, substrate, peripheral area, signal, and transistor of Lius; i.e., a third transistor of a gate driver controls a signal of Lius, where the signal is to the first and second transistors of Liu as modified; also, it would have been obvious to include the third transistor as claimed since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to select electronic and sensing units), to select electronic and sensing units. (Lius: [0025]).
Regarding claim 11, Liu as modified by Kawase and Lius teaches:
The electronic device as claimed in claim 10, further comprising a fourth transistor disposed on the substrate, wherein the fourth transistor is electrically connected between the first transistor and the second transistor, and the signal is transmitted to the first transistor through a fourth transistor (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to control selecting between an electronic unit and a sensing unit).
Regarding claim 13, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 1, further comprising an electronic unit driving circuit (PX11 in FIGs. 1 and 4 of Liu) disposed on the substrate, the electronic unit driving circuit including a second transistor (M5 in FIG. 4) electrically connected to the electronic unit, wherein the electronic device further includes an active area (101 in FIG. 2 of Liu) and a peripheral area (102), the sensor unit driving circuit and the electronic unit driving circuit are disposed in the active area (Liu: FIGs. 1-2, 4, and 6, “[0030]... The substrate 100 [of the electronic device 10] includes a non-peripheral area 101 and a peripheral area 102.... The pixel unit[] PX11... [of the non-peripheral area 101 of the substrate 100]... can be, for example, organic light emitting diode (OLED)....”, “[0031] There... [is an] integration unit[] U11... in the non-peripheral area 101 [of the substrate 100].... [C]omponents for sensing and display, including the pixel PX11... and a sensing unit PD11... are integrated within the integration unit U11....”, “[0046] The pixel unit PX11 is corresponding to the transistor M5....”, see also FIG. 8 and FIG. 17 (electronic unit driving circuit PX11_16, second transistor M8, and electronic unit OD11)).
However, it is noted that Liu as modified by Kawase does not teach:
wherein the electronic device further includes a third transistor and a fourth transistor respectively disposed on the substrate, the third transistor and the fourth transistor are disposed in the peripheral area, the third transistor controls a first signal to the first transistor, and the fourth transistor controls a second signal to the second transistor.
Lius teaches:
wherein an electronic device (1 in FIG. 1) further includes a third transistor (of 122 in FIG. 4) and a fourth transistor (of 120 in FIG. 4) respectively disposed on a substrate (14), the third transistor and the fourth transistor are disposed in a peripheral area (12), the third transistor controls a first signal to a first transistor (of Ps(1,1)), and the fourth transistor controls a second signal to a second transistor (of Pd(1,1)) (Lius: FIGs. 1 and 4, [0024] (including: “... The display device 1 [in FIG. 1] has a display region 10 and a side region 12 adjacent to the display region 10....”), “[0025] (including: “.... The display gate driver 120 may be coupled to a portion of the plurality of display units 100 and may comprise a plurality of first thin-film transistors to select display units 100 via corresponding display driving units 102.... Similarly, the sensor gate driver 122 may be coupled to a portion of the plurality of sensing units 104 and may comprise a plurality of second thin-film transistors to select sensing units 104 via corresponding sensor driving units 106.... At least a portion of the plurality of first thin-film transistors and at least a portion of the plurality of second thin-film transistors are disposed in the side region 12.”), “[0027]... FIG. 2 shows that the display device 1 further comprises an array substrate 14....”, “[0030]... [T]he display gate driver 120 and the sensor gate driver 122 [in FIG. 4] share the side region 12....”, and [0031] (including: “... The display gate driver 120 [in FIG. 4] may be coupled to display sub-pixels Pd(M,N) in a first row via a display gate line Ldr[1].... Likewise, the sensor gate driver 122 may be coupled to sensor pixels Ps(P,Q) in a first row via a sensor gate line Lsr[1].... The control circuit 128 is coupled to the display gate driver 120 and the sensor gate driver 122... to select each row of the display sub-pixels Pd(M,N) and each row of the sensor pixels Ps(P,Q), respectively....”), see also FIG. 5, FIG. 9 (third transistor M3, and fourth transistor M4), FIG. 10, [0032], and [0036]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Lius, such that Liu as modified teaches: further comprising an electronic unit driving circuit disposed on the substrate, the electronic unit driving circuit including a second transistor electrically connected to the electronic unit, wherein the electronic device further includes a third transistor and a fourth transistor respectively disposed on the substrate, wherein the electronic device further includes an active area and a peripheral area, the sensor unit driving circuit and the electronic unit driving circuit are disposed in the active area, the third transistor and the fourth transistor are disposed in the peripheral area, the third transistor controls a first signal to the first transistor, and the fourth transistor controls a second signal to the second transistor (electronic and sensor unit driving circuits, substrate, second transistor, electronic unit, electronic device, active and peripheral areas, and first and second transistors of Liu as modified combined with the electronic device, third and fourth transistors, substrate, peripheral area, first and second signals, and first and second transistors of Lius), to provide image display and fingerprint sensing.
Regarding claim 14, Liu as modified by Kawase and Lius teaches:
The electronic device as claimed in claim 13, wherein the first signal is a reset signal, and the second signal is a switch signal (Liu: the second signal is as claimed; see FIG. 4 and [0047] including (“The control terminal of the transistor M5 is coupled to the scan driver 25 to receive the row selecting signal SC[1].....”, see also FIG. 17, [0030], [0074], and [0076]; it would have been obvious to include the first signal as claimed since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for circuit reset).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Kawase, in further view of Kim et al. in US 2015/0123084 A1 (hereinafter Kim).
Regarding claim 16, Liu as modified by Kawase teaches:
The electronic device as claimed in claim 1, further comprising a second conductive layer (600 in FIG. 6 of Liu) and an electronic unit driving circuit (PX11 in FIGs. 1 and 4) respectively disposed on the substrate, wherein the second conductive layer includes a second gate (600(G2) in FIG. 8), the electronic unit driving circuit includes a second transistor (M5 in FIG. 4), (Liu: FIGs. 1-2, 4, 6, and 8, “[0030]... [T]he non-peripheral area 101 [of the substrate 100] includes pixel unit[] PX11....”, “[0031] There... [is an] integration unit[] U11... in the non-peripheral area 101 [of the substrate 100].... [C]omponents for sensing and display, including the pixel PX11... and a sensing unit PD11... are integrated within the integration unit U11....”, “[0046] The pixel unit PX11 is corresponding to the transistor M5....”, and “[0053]... [T]he transistor M1... has a double gate structure, and includes a control terminal G1 and a control terminal G2.... [T]he double gate structure may be, for example, different conductive layers (e.g., the conductive layers 600, 601) located in opposite upper and lower sides of the same semiconductor layer to control the corresponding semiconductor layer....”).
However, it is noted that Liu as modified by Kawase does not teach:
the second transistor has the second gate, and the second gate is electrically connected to the electronic unit.
Kim teaches:
a second transistor (22 in FIG. 4) has a second gate (224), and the second gate is electrically connected to an electronic unit (25) (Kim: FIGs. 2 and 4, “[0061] The organic light-emitting display apparatus 1 includes a light-emitting device 25 in a pixel area PXL,... a second transistor 22 in a second transistor area TR2.... Referring to FIGS. 4 and 2,... the second transistor 22 corresponds to the switching transistor M1....”, and “[0089]... [T]he second transistor 22 additionally includes the auxiliary gate electrode 227.... The auxiliary gate electrode 227, may form dual wiring by being connected to the gate electrode 224....”, see also [0042]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Kim, such that Liu as modified teaches:
further comprising a second conductive layer and an electronic unit driving circuit respectively disposed on the substrate, wherein the second conductive layer includes a second gate, the electronic unit driving circuit includes a second transistor, the second transistor has the second gate, and the second gate is electrically connected to the electronic unit (second conductive layer, electronic unit driving circuit, substrate, second gate, second transistor, and electronic unit of Liu as modified combined with the second transistor, second gate, and electronic unit of Kim; i.e., the second transistor of Liu as modified is the second transistor of Kim), to reduce resistance. (Kim: [0089]).
Regarding claim 17, Liu as modified by Kawase and Kim teaches:
The electronic device as claimed in claim 16, wherein a shape of the second gate is different from the shape of the line segment (Liu: shape of second gate 600(G2); see FIG. 8; claim 16 above; i.e., shape of the second gate of Liu, where the second gate is that of Kim, is different as claimed).
Regarding claim 18, Liu as modified by Kawase and Kim teaches:
The electronic device as claimed in claim 17, wherein a shspe of the second gate being different from the shape of the line segment indicates that a width of the second gate is smaller than a width of the line segment (a width of the second gate is larger than a width of the line segment; Liu: see FIG. 8; claims 16-17 above; it would have been obvious to include the claimed features as obvious to try of one of a finite number of identified, predictable, and ascertainable group of smaller, larger, and equal to to provide second gate and line segment widths for image display for an electronic device with a reasonable expectation of success).
Regarding claim 19, Liu as modified by Kawase and Kim teaches:
The electronic device as claimed in claim 16, wherein the first transistor and the second transistor have semiconductors of different materials (Liu: the first transistor and the second transistor have semiconductors of materials; FIG. 6, “[0052] Regions of transistors M1... [and] M5 are, for example, dashed boxes as shown in FIG. 6, and each transistor includes a semiconductor layer 63....”, and “TABLE... The material of the semiconductor layer may layer include, but is not limited to, Si (amorphous, polycrystalline, single crystal).... The material of the semiconductor layer may also include, but is not limited to, metal oxides....”; it would have been obvious to include the claimed features as obvious to try of one of a finite number of identified, predictable, and ascertainable group of same and different to provide transistors for use in image display and fingerprint sensing, and since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide transistors for use in image display and fingerprint sensing).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Kawase, in further view of Kim, and in further view of Hwang et al. in US 2022/0148516 A1 (hereinafter Hwang).
Regarding claim 20, Liu as modified by Kawase and Kim teaches:
The electronic device as claimed in claim 16.
However, it is noted that Liu as modified by Kawase and Kim does not teach:
further comprising an additional conductive layer disposed on the substrate, wherein the additional conductive layer includes a connection portion, and the first gate and the second gate are electrically connected through the connection portion.
Hwang teaches:
an additional conductive layer disposed on a substrate (SUBS in FIG. 5), wherein the additional conductive layer includes a connection portion, and a first gate (GE1) and a second gate (GE2) are electrically connected through the connection portion (Hwang: FIGs. 4-5, “[0090]... [A]s shown in FIG. 5, the first metal layer is disposed on the substrate SUBS of the display panel 10....”, “[0091] The first metal layer includes... the bottom gate electrode GE2....”, “[0097]... [T]he top gate electrode GE1 of the... [transistor] DT is formed of a second metal layer pattern disposed on the gate insulating layer GI.”, and “[0099] The top gate electrode GE1 and the bottom gate electrode GE2 of the... [transistor] DT are connected through a first contact hole CH1 to thereby realize a double gate structure. The first contact hole CH1 penetrates the gate insulating layer GI and the buffer layer BUF to expose the bottom gate electrode GE2. The buffer layer BUF, the semiconductor layer ACT, and the gate insulating layer GI are stacked between the top gate electrode GE1 and the bottom gate electrode GE2.”, see also FIG. 2).
Before the effective filing date of the claimed invention, it would have been obvious to include: the features taught by Hwang, such that Liu as modified teaches: further comprising an additional conductive layer disposed on the substrate, wherein the additional conductive layer includes a connection portion, and the first gate and the second gate are electrically connected through the connection portion (substrate and first and second gates of Liu as modified combined with the additional conductive layer, substrate, connection portion, and first and second gates of Hwang), to provide a transistor with a double gate structure. (Hwang: [0099]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 7/30/26
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