DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai; Shin et al. (US Publication #US 20180208237 A1; hereinafter Kumagai) in view of Kitamoto; Hiroshi (US Publication #US 20170229983 A1; hereinafter Kitamoto).
Regarding claim 1, Kumagai teaches
An abnormality detection circuit (fig.5 #100) configured to detect abnormalities of a first half bridge (par.43 “an FET bridge having upper-stage FETs (High side) and lower-stage FETs (Low side)) as semiconductor switching devices.”; the high side is interpreted as a half bridge) including a first switching element (fig.5 FET 1) and a second switching element (fig.5 any of FET 2 to 6), the abnormality detection circuit comprising:
a series circuit (fig.5 comprises a series circuit) of a first switch (fig.5 dark suppression switch #130) and a first resistor (fig.6 R121) provided between a first node (fig.5 shows numerous nodes), and a second node (fig.5 shows numerous nodes used as connection nodes) configured so as to have a first constant voltage applied thereto (fig.5 shows GND node configured to have constant voltage applied); and
a first comparator (comparator 117) configured so as to compare a voltage corresponding to a voltage of the first node with a first reference voltage (par.52).
Kumagai fails to explicitly teach which is a connection node for the first switching element and the second switching element.
Kitamoto does teach which is a connection node for the first switching element and the second switching element (par.41 “A node (that may be referred to as a middle point or a connection point) Pu between the upper-arm switching element T1 and the lower-arm switching element T2 is connected to a phase coil 20u as an output terminal for the U phase”).
It would have been prima facie obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to have modified Kumagai to include the teachings of Kitamoto; which would provide a motor control apparatus that uses a simple configuration to enable monitoring of a circuit supplying a negative voltage used to control switching elements as disclosed by Kitamoto (paragraph 9).
Regarding claim 2, Kumagai in view of Kitamoto teaches the abnormality detection circuit according to claim 1 and Kumagai further teaches further configured so as to detect not only abnormalities of the first half bridge but also abnormalities of a second half bridge (par.43 “an FET bridge having upper-stage FETs (High side) and lower-stage FETs (Low side)) as semiconductor switching devices.”; the low side is interpreted as the 2nd half bridge) including a third switching element (fig.5 any of FET 2 to 6) and a fourth switching element (fig.5 any of FET 2 to 6), the abnormality detection circuit further comprising:
a second resistor provided between a third node, which is a connection node for the third switching element and the fourth switching element, and a fourth node configured so as to have a second constant voltage applied thereto (resistance R121; the resistance voltage dividing circuit 120 in fig.6 is described collectively, but in fig.5 wiring is connected from each FET, three types of divided voltage are output from the resistance voltage dividing circuit 120, and it is inherent there’s a 2nd resistor); and
a second comparator (par.52 teaches three comparators) configured so as to compare a voltage corresponding to a voltage of the third node with a second reference voltage (par.52).
Regarding claim 3, Kumagai in view of Kitamoto teaches the abnormality detection circuit according to claim 2, Kumagai further teaches further comprising a second switch connected in series to the second resistor (fig.5-7 inherently teaches a 2nd switch connected in series to the 2nd resistor).
Regarding claim 4, Kumagai in view of Kitamoto teaches the abnormality detection circuit according to claim 2, Kumagai further teaches wherein a load provided between the first half bridge and the second half bridge has a resistance smaller than a resistance of the first resistor as well as than a resistance of the second resistor (par.67-68 inherently teaches load having smaller resistance through upper and lower stage FETs having larger values).
Regarding claim 17, Kumagai in view of Kitamoto teaches a motor drive device which comprises the abnormality detection circuit according to claim 1 (Kumagai fig.3 shows #37 inverter; inverters act as motor drive devices).
Regarding claim 18, Kumagai teaches a motor system comprising:
a motor (fig.3 #20 motor); and
Kumagai in view of Kitamoto teaches the motor drive device according to claim 17, which is configured so as to drive the motor (fig.3 #37).
Regarding claim 19, Kumagai in view of Kitamoto teaches a vehicle which comprises the motor system according to claim 18 (par.43).
Allowable Subject Matter
Claims 5-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art does not teach or suggest, in combination with the rest of the limitation of claim 5,
“… further comprising a third resistor configured so that a voltage corresponding to a voltage of the first node is applied to a first end of the third resistor and a ground voltage is applied to a second end of the third resistor, wherein the third resistor has a resistance larger than a resistance of the first resistor.”
Claims 9 and 13 are also objected to due to their dependence on claim 5.
Regarding claim 6, the prior art does not teach or suggest, in combination with the rest of the limitation of claim 6,
“… further comprising a third resistor configured so that a voltage corresponding to a voltage of the first node is applied to a first end of the third resistor and a ground voltage is applied to a second end of the third resistor, wherein the third resistor has a resistance larger than a resistance of the first resistor.”
Claims 10 and 14 are also objected to due to their dependence on claim 6.
Regarding claim 7, the prior art does not teach or suggest, in combination with the rest of the limitation of claim 7,
“… further comprising a third resistor configured so that a voltage corresponding to a voltage of the first node is applied to a first end of the third resistor and a ground voltage is applied to a second end of the third resistor, wherein the third resistor has a resistance larger than a resistance of the first resistor.”
Claims 11 and 15 are also objected to due to their dependence on claim 7.
Regarding claim 8, the prior art does not teach or suggest, in combination with the rest of the limitation of claim 8,
“… further comprising a third resistor configured so that a voltage corresponding to a voltage of the first node is applied to a first end of the third resistor and a ground voltage is applied to a second end of the third resistor, wherein the third resistor has a resistance larger than a resistance of the first resistor.”
Claims 12 and 16 are also objected to due to their dependence on claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
US 7466139 B2; Furukawa; Kimihiko is a Method to determine current detection circuit failure.
US 20110062996 A1; CHANG; Chun-Chi et al. is a power on detection circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARL F.R. TCHATCHOUANG whose telephone number is (571)272-3991. The examiner can normally be reached Monday - Friday 8:00am -5:00am.
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/CARL F.R. TCHATCHOUANG/Examiner, Art Unit 2858
/ALVARO E FORTICH/Primary Examiner, Art Unit 2858
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