DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuno et al. (US 2014/0361917).
Regarding claim 1, Matsuno et al. (Figs. 1 and 10-11) discloses an apparatus (flash ADC of Fig. 1 or 10; para. [0022]) comprising:
first voltage comparator (101) having an input (+) and an output (A1p/A1n) (para. 25);
second voltage comparator (102) having an input (+) and an output (A2p/A2n) (para. 26), the input of the second voltage comparator coupled to the input of the first voltage comparator (to receive an input Vin); and
delay comparator (121; para 29) having a first input and a second input, the first input of the delay comparator coupled to the output of the first voltage comparator (101), the second input of the delay comparator coupled to the output of the second voltage comparator (102) (para. 29 and 71).
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Michel (US 5,420,587).
Regarding claim 1, Michel discloses an apparatus (Fig. 1) comprising:
first voltage comparator (C1) having an input (+) and an output (17);
second voltage comparator (C2) having an input (+) and an output (18), the input of the second voltage comparator (C2) coupled to the input of the first voltage comparator (C1) (to receive an input Vin); and
delay comparator (C23 of second stage comparators 22) having a first input and a second input (each of the comparators 22 has multiple inputs), the first input of the delay comparator coupled to the output of the first voltage comparator (C1), the second input of the delay comparator coupled to the output of the second voltage comparator (C2) (col. 4, lines 14-43).
Regarding claim 2, Michel (Fig. 1) discloses the apparatus of claim 1, wherein the delay comparator (C23) is first delay comparator, and the apparatus further comprising: second delay comparator (C24) having a first input and a second input; and third delay comparator (C25) having a first input and a second input, the first input of the third delay comparator coupled to the first input of the first delay comparator and the first input of the second delay comparator, the second input of the third delay comparator coupled to the second input of the first delay comparator and the second delay comparator (Fig. 1 shows some inputs of these comparators are tied together; col. 4, lines 60-66).
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3-6, neither Matsuno nor Michel discloses or suggests the recitation “first voltage-controlled delay circuitry having a first input, a second input, and an output, the first input of the first voltage-controlled delay circuitry coupled to the output of the first voltage comparator, the output of the first voltage-controlled delay circuitry coupled to the first input of the delay comparator; second voltage-controlled delay circuitry having a first input, a second input, and an output, the first input of the second voltage-controlled delay circuitry coupled to the output of the second voltage comparator, the output of the second voltage-controlled delay circuitry coupled to the second input of the delay comparator; and offset voltage control circuitry having a first output and a second output, the first output of the offset voltage control circuitry coupled to the second input of the first voltage-controlled delay circuitry, the second output of the offset voltage control circuitry coupled to the second input of the second voltage-controlled delay circuitry”.
Regarding claims 7-9, neither Matsuno nor Michel discloses or suggests the recitation “the input of the first voltage comparator is a first input, the first voltage comparator further has a second input and a third input, the input of the second voltage comparator is a first input, the second voltage comparator further has a second input and a third input, and the apparatus further comprising voltage reference generation circuitry having a first output, a second output, a third output, and a fourth output, the first output of the voltage reference generation circuitry coupled to the second input of the first voltage comparator, the second output of the voltage reference generation circuitry coupled to the third input of the first voltage comparator, the third output of the voltage reference generation circuitry coupled to the second input of the second voltage comparator”.
Regarding claims 10-11, neither Matsuno nor Michel discloses or suggests the recitation “the first voltage comparator further has a sign output, the second voltage comparator further has a sign output, and the delay comparator further has a sign output, and the apparatus further comprising: switch having a terminal; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC coupled to the sign output of the first voltage comparator, the sign output of the second voltage comparator, and the sign output of the delay comparator; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the DAC; and amplifier having an input coupled to the second input of the first voltage comparator, the second input of the second voltage comparator, the terminal of the switch, and the second terminal of the capacitor”.
Regarding claims 12-15, neither Matsuno nor Michel discloses or suggests the recitation “reference generation circuitry [210] having a first output and a second output; a voltage comparator stage [220] having a first input, a second input, a first output, and a second output, the first input of the voltage comparator stage coupled to the first output of the reference generation circuitry, the second input of the voltage comparator stage coupled to the second output of the reference generation circuitry…”.
Regarding claims 17-20, neither Matsuno nor Michel discloses or suggests the recitation “a voltage comparator stage having an input, a sign output, a first delay output, and a second delay output; and a delay comparator stage having a first input, a second input, and a sign output, the first input of the delay comparator stage coupled to the first delay output of the voltage comparator stage, the second input of the delay comparator stage coupled to the second delay output of the voltage comparator stage…”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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