Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 18-36 are rejected under 35 U.S.C. 103 as being unpatentable over Bak et al. (US 20170104974 A1) in view of Ra et al. (US 20120163165 A1).
Claim 18 Bak teaches a system for routing an input serial digital interface (SDI) signal, the system comprising:
a midplane; (Bak, FIG. 1, ¶0116, IP switching/routing apparatus 100) and
a controller coupled to the midplane, (Bak, FIG. 1, ¶0145, synchronization control module 140) the controller transmitting control signals to control the operation of the midplane; (Bak, ¶0065, providing synchronization signals, i.e. midplane control signals)
the midplane comprising an address inserting module (Examiner interprets “an address inserting module” as merely the midplane as configured as described) configured to:
receive a packetized media stream having a plurality of packets and an associated source address; (Bak, FIG. 1, ¶0052, receiving video signals, i.e. packetized media, associated with sources, sources inherently have addresses)
reproduce the packetized media stream to generate one or more separate packetized media streams, each of the one or more separate packetized media streams to be routed to a plurality of destinations; (Bak, FIG. 1, ¶0052, convert the video signals into IP packets, ¶0062, each to be transmitted to destinations 300)
for each of the separate packetized media streams:
determine a destination address for the separate packetized media stream based on control signals transmitted by the controller; (Bak, ¶0086, ¶0086, wherein the synchronization information provides destination 300 information for packets) and
the midplane further comprising a routing switch coupled to the address inserting module, the routing switch being configured to: receive the processed packet; (Bak, FIG. 1, IP switching/routing module 120, ¶0081, receiving the preprocessed IP packets) and
route the processed packet to an output port based on the destination address and the control signals from the controller. (Bak, FIG. 1, ¶0081-¶0083, routing the processed ports to an output port based on the control signals and address)
However, Bak does not explicitly teach for each packet in a separate packetized media stream, update the corresponding packet header with the destination address to generate a corresponding processed packet.
From a related technology, Ra teaches for each packet in a separate packetized media stream, update the corresponding packet header with the destination address to generate a corresponding processed packet. (FIG. 5, ¶0085, header processor 534 removes the internal header and updates the destination mac address)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed inventions to modify the teachings of Bak to incorporate the teachings of Ra to more effective updates destination addresses and streamline communication efficiency.
Claim 19 Bak in view of Ra teaches Claim 18, and further teaches determine addressing rules, the addressing rules corresponding to the plurality of destinations for the packetized media stream; (Bak, ¶0065, providing synchronization signals, i.e. midplane control signals, wherein the synchronization signals are the addressing rules) generate the control signals corresponding to the addressing rules; (Bak, ¶0065, generating the control signals from the synchronization signals) and transmit the control signals to the midplane. (Bak, ¶0065, transmitting control signals)
Claim 20 Bak in view of Ra teaches Claim 19, and further teaches wherein the controller is configured to determine the addressing rules based on traffic load information received from the routing switch. (Bak, ¶0065, providing synchronization signals based on traffic information received)
Claim 21 Bak in view of Ra teaches Claim 19, and further teaches wherein the controller is configured to determine the addressing rules based on content requirements of downstream devices. (Bak, ¶0065, providing synchronization signals, i.e. midplane control signals based on device requirements)
Claim 22 Bak in view of Ra teaches Claim 18, and further teaches identify the source address corresponding to the packetized media stream. (Ra, FIG. 4, ¶0060, acquires source address for the packet stream)
Claim 23 Bak in view of Ra teaches Claim 22, and further teaches wherein the address inserting module is configured to append the destination address to the source address of the packet header. (Ra, FIG. 5, ¶0085, header processor 534 removes the internal header and updates the destination mac address)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed inventions to modify the teachings of Bak to incorporate the teachings of Ra to more effective updates destination addresses and streamline communication efficiency.
Claim 24 Bak in view of Ra teaches Claim 22, and further teaches wherein the address inserting module is configured to replace the source address of the packet header with the destination address. (Ra, FIG. 5, ¶0085, header processor 534 removes the internal header and updates the destination mac address)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed inventions to modify the teachings of Bak to incorporate the teachings of Ra to more effective updates destination addresses and streamline communication efficiency.
Claim 25 Bak in view of Ra teaches Claim 18, and further teaches wherein the midplane is coupled to at least one input card and at least one output card. (Bak, FIG. 3, ¶0067, a midplane coupled to input card 110 and output card 130)
Claim 26 Bak in view of Ra teaches Claim 25, and further teaches wherein the at least one input card is configured to:
receive the input serial digital interface (SDI) signal at an input SDI port of the at least one input card; (Bak, FIG. 1, ¶0052, receive SDI input)
process the input SDI signal to generate the packetized media stream; (Bak, FIG. 1, ¶0052, convert the video signals into IP packets) and
transmit the packetized media stream to the midplane. (Bak, FIG. 1, ¶0055, received by the midplane)
Claim 27 Bak in view of Ra teaches Claim 25, and further teaches wherein the at least one output card is configured to:
receive the processed packet at an input IP port of the at least one output
card; (Bak, FIG. 1, ¶0063, received packets by the output card)
process the processed packet to generate a corresponding output SDI signal; (Bak, ¶0063, convert to SDI signal) and
provide the output SDI signal at an output SDI port. (Bak, ¶0063, output SDI signal)
Claim 28 Bak teaches a system for routing an input serial digital interface (SDI) signal, the system comprising:
a midplane; (Bak, FIG. 1, ¶0116, IP switching/routing apparatus 100) and
a controller coupled to the midplane, (Bak, FIG. 1, ¶0145, synchronization control module 140) the controller transmitting control signals to control the operation of the midplane; (Bak, ¶0065, providing synchronization signals, i.e. midplane control signals)
the midplane comprising an address inserting module (Examiner interprets “an address inserting module” as merely the midplane as configured as described) configured to:
receive a packetized media stream having a plurality of packets and an associated source address; (Bak, FIG. 1, ¶0052, receiving video signals, i.e. packetized media, associated with sources, sources inherently have addresses)
determine a destination address for the separate packetized media stream based on control signals transmitted by the controller; (Bak, ¶0086, ¶0086, wherein the synchronization information provides destination 300 information for packets) and
the midplane further comprising a routing switch coupled to the address inserting module, the routing switch being configured to: receive the processed packet; (Bak, FIG. 1, IP switching/routing module 120, ¶0081, receiving the preprocessed IP packets) and
route the processed packet to an output port based on the destination address and the control signals from the controller. (Bak, FIG. 1, ¶0081-¶0083, routing the processed ports to an output port based on the control signals and address)
However, Bak does not explicitly teach for each packet in a separate packetized media stream, update the corresponding packet header with the destination address to generate a corresponding processed packet.
From a related technology, Ra teaches for each packet in a separate packetized media stream, update the corresponding packet header with the destination address to generate a corresponding processed packet. (FIG. 5, ¶0085, header processor 534 removes the internal header and updates the destination mac address)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed inventions to modify the teachings of Bak to incorporate the teachings of Ra to more effective updates destination addresses and streamline communication efficiency.
Claim 29-31 are taught by Bak in view of Ra as described for Claims 19-21.
Claim 32-36 are taught by Bak in view of Ra as described for Claims 23-27.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER PALACA CADORNA whose telephone number is (571)270-0584. The examiner can normally be reached M-F 10:00-7:00.
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/CHRISTOPHER P CADORNA/Examiner, Art Unit 2444
/JOHN A FOLLANSBEE/Supervisory Patent Examiner, Art Unit 2444
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