DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Classifying Load and Store Instructions for Memory Renaming”, henceforth referred to as Reinman et al.
Consider claim 1, Reinman et al. discloses a data processing apparatus comprising: prediction circuitry configured to store a plurality of mappings from instructions to payloads; and query circuitry configured to respond to a reference to one of the instructions provided as at least part of an input by outputting one of the payloads that maps to the one of the instructions, wherein the payloads comprise one of a plurality of predictions and a prediction type configured to indicate which of a plurality of data speculation techniques the one of a plurality of predictions relates; and the prediction circuitry is configured, for each of the instructions, to store the prediction type as one of a plurality of different prediction types (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store.).
Consider claim 2, Reinman et al. discloses the data processing apparatus according to claim 1, wherein each of the instructions is a memory access instruction (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses that loads and stores are tracked for determining which type of prediction mechanism best applies).
Consider claim 3, Reinman et al. discloses the data processing apparatus according to claim 1, wherein the data speculation techniques include a memory rename operation and a data value prediction operation (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative.).
Consider claim 4, Reinman et al. discloses the data processing apparatus according to claim 3, wherein in the memory rename operation, the one of the instructions is predicted as a load instruction that loads data from a memory address and the data is predicted to be produced by a corresponding producer instruction, which is a store instruction configured to store the data to the memory address prior to the instruction being executed (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that uses memory renaming as claimed.).
Consider claim 5, Reinman et al. discloses the data processing apparatus according to claim 3, wherein the plurality of predictions includes: an indication of data that is predicted to be used by a value predictable instruction, and an indication of a previous producer instruction whose data is to be used by a memory renamable instruction (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative.).
Consider claim 6, Reinman et al. discloses the data processing apparatus according to claim 4, wherein the indication of the data is any one of: an indication of an index of data storage circuitry where the data can be found, and the data (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism.).
Consider claim 7, Reinman et al. discloses the data processing apparatus according to claim 2, comprising: determination circuitry configured to perform a determination of which of the data speculation techniques an instruction should be subject to (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative.); and training circuitry configured to update or allocate an entry in the prediction circuitry in respect of the instruction, based on the determination (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism).
Consider claim 8, Reinman et al. discloses the data processing apparatus according to claim 3, comprising: determination circuitry configured to perform a determination of whether an instruction should be subject to the memory rename operation and whether the instruction should be subject to the data value prediction operation (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative.); and training circuitry configured to update or allocate an entry in the prediction circuitry in respect of the instruction, based on the determination (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism).
Consider claim 9, Reinman et al. discloses the data processing apparatus according to claim 7, wherein the training circuitry is configured to allocate an entry to the prediction circuitry based on an allocation condition, which differs for the plurality of data speculation techniques (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism).
Consider claim 10, Reinman et al. discloses the data processing apparatus according to claim 7, wherein the determination circuitry is configured to determine which of the data speculation techniques an instruction should be subject to based on a hierarchy; and at least one of the data speculation techniques is determined based on a further condition being met (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store.).
Consider claim 11, Reinman et al. discloses the data processing apparatus according to claim 7, wherein the training circuitry is configured to filter accesses to the prediction circuitry made in respect of a given instruction based on an indication of whether the given instruction is being trained or is trained (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism).
Consider claim 12, Reinman et al. discloses the data processing apparatus according to claim 7, wherein the training circuitry is configured to perform training in respect of the instruction using a predicted value comprising a determined payload comprising a determined prediction type and a determined prediction (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store.).
Consider claim 13, Reinman et al. discloses the data processing apparatus according to claim 1, wherein the prediction circuitry is configured to implement a replacement policy, which biases replacing mappings based on the prediction type (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism. Mappings can be adjusted based on the heuristics results.).
Consider claim 14, Reinman et al. discloses the data processing apparatus according to claim 8, wherein when the training circuitry replaces the payload in one of the mappings with a current payload associated with the instruction, both the prediction type and prediction are replaced (Sections: 5, 5.1, table 1, Reinman et al. discloses that profile data for each load is maintained and heuristics are used to refine the candidate predictions for each type of prediction mechanism. Mappings can be adjusted based on the heuristics results.).
Consider claim 15, Reinman et al. discloses the data processing apparatus according to claim 1, wherein the input comprises an instruction context; and the plurality of mappings is a plurality of mappings from the instructions and instruction contexts to the payloads such that one of the instructions may be mapped to at least two of the payloads by providing inputs with different ones of the instruction contexts (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store.).
Consider claim 16, Reinman et al. discloses the data processing apparatus according to claim 1, wherein when the predictor compares payloads, a match between the payloads requires a match between prediction type and prediction (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to match which type of prediction mechanism best applies to a particular load/store.).
Consider claim 19, Reinman et al. discloses a data processing method comprising: storing a plurality of mappings from instructions to payloads; responding to a reference to one of the instructions provided as at least part of an input by outputting one of the payloads that maps to the one of the instructions, wherein the payloads comprise one of a plurality of predictions and a prediction type configured to indicate which of a plurality of data speculation prediction techniques the one of a plurality of predictions prediction type relates; and for each of the instructions, the prediction type is stored as one of a plurality of different prediction types (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store.).
Consider claim 20, Reinman et al. discloses a non-transitory computer-readable medium storing computer-readable code for fabrication of the data processing apparatus of claims 1 (introduction, sections: 2.3, 3, 3.1.1, 3.1.2, Reinman et al. discloses a system that determines prediction mechanisms for each load, which can be between memory renaming, value prediction or non-speculative. Load marking hints and memory renaming tags are used in conjunction with a store cache, store/load cache, value file and confidence mechanism. The hints and tags are used to determine which type of prediction mechanism best applies to a particular load/store. Code about how the system operates is considered code for/related to fabrication.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Classifying Load and Store Instructions for Memory Renaming”, henceforth referred to as Reinman et al. as applied to claim 1 above, and further in view of official notice.
Consider claims 17 and 18, Reinman et al. discloses a system comprising: the data processing apparatus according to claim 1, but Reinman et al. does not go into specific detail as to the exact components of a system that can perform the claimed operations. However, these claims describes components such as chips, multiple boards and at least one system component and at least one product component. These are all extremely common components of any conventional personal computer/laptop where display screens, a mouse, a keyboard, multiple interconnected boards such as motherboards, graphics, sound and network boards and chips such as CPUs and GPUs. Therefore, the examiner is taking official notice to the use of a conventional personal computer/laptop in conjunction with the system described in Reinman et al.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the system of Reinman et al. to be performed on a conventional computer because conventional computers are readily available, easy to use and cost effective.
Response to Arguments
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
The applicant first argues that it is unclear where Reinman teaches prediction circuitry configured to store a plurality of mappings from instructions to payloads. This limitation requires circuitry that stores some form of a mapping (connection/identification) between an instruction (load/store) and the payload. The payload is claimed to comprise one of (either) a plurality of predictions or a prediction type. Reinman discloses a system where loads have load markings in the form of load marking hints for identifying loads suitable for renaming and MRT tags that are mapped to the loads/stores. These MRT tags are used to index into the Value File for tagged stores and loads, the Value File being for rename/value prediction. Loads can have the three types: Rename, Value Predict and Non-Speculative and the MRT tags can indicate rename-store, rename-load and value-predict-load.
The applicant next argues that the claims recite that the payloads comprise one of a plurality of predictions and a prediction type configured to indicate which of a plurality of data speculation techniques the one of a plurality of predictions relates. Reinman does not disclose the claimed payloads because Reinman merely indicates which prediction mechanism to use so there is no need to store a payload to indicate a prediction type. Reinman discloses a system where loads have load markings in the form of load marking hints for identifying loads suitable for renaming and MRT tags that are mapped to the loads/stores. These MRT tags are used to index into the Value File for tagged stores and loads, the Value File being for rename/value prediction. Loads can have the three types: Rename, Value Predict and Non-Speculative and the MRT tags can indicate rename-store, rename-load and value-predict-load. These prediction mechanisms are considered prediction types.
The applicant further argues that the claimed prediction type that is stored "a prediction type configured to indicate which of a plurality of data speculation techniques the one of a plurality of predictions relates." Again, there is no need in Reinman for a prediction type to be stored in prediction circuitry. As stated in item 27 above, Reinman discloses a system where loads have load markings in the form of load marking hints for identifying loads suitable for renaming and MRT tags that are mapped to the loads/stores. These MRT tags are used to index into the Value File for tagged stores and loads, the Value File being for rename/value prediction. Loads can have the three types: Rename, Value Predict and Non-Speculative and the MRT tags can indicate rename-store, rename-load and value-predict-load. These prediction mechanisms are considered prediction types.
Finally, the applicant argues that the claimed prediction circuitry is not disclosed in Reinman, query circuitry that queries such prediction circuitry also is not disclosed in Reinman. Reinman discloses the claimed function that these circuits perform as rejected and explained in items 26-28 above and therefore the hardware supporting these functions are considered the claimed circuitry.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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