DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Jeong et al. (Pub No. US 2015/0227187).
Regrading Claim 1 Jeong discloses: an input/output module [Fig.1A and 1B] comprising: a first interface, [Fig.1, item 230] wherein the I/O module is configured to send first process data to a control module via the first interface and/or to receive second process data from the control module via the first interface; [[0045] [0050], HSSI 230 includes the transmitter 231 and the receiver 232. For example, each of the transmitter 231 and the receiver 232 may be embodied in a structure of transmitting differential signals. The HSSI 230 may transmit or receive an instruction and/or data to or from a device side second interface (DSSI) 340 through signal lines 130-1 and 130-2 included in the second interface 130] and a second interface, [Fig.1, item 220] wherein the I/O module is further configured to send a first signal indicating availability of the first process data to the control module via the second interface and/or to receive a second signal indicating availability of the second process data from the control module via the second interface, [[0047] he transmitter 221 of the HSFI 220 may transmit a first interface signal FIS which may control an operation state of the data storage device 300 to the data storage device 300 through a signal transmission line 110-1. The first interface signal FIS includes a first signal or a second signal. For example, the signal transmission line 110-1 may be embodied in a cable. Examples of each of the first signal and the second signal include a data packet or a data pattern.] wherein the I/O module is configured to cause the first interface to transition from a power saving mode, in which the first interface is not ready to receive data, to a communication mode, in which the first interface is ready to receive data, when the first interface is in the power saving mode and the second signal is received via the second interface. [Fig.1 and Fig.2,[ [0048], the data storage device 300 may perform an entry into a power saving mode in response to the first signal, and perform an exit from the power saving mode in response to the second signal. [0059] [0062] the first signal 111 may be a signal which indicates an entry into a power saving mode or a sleep state. For example, the first signal 111 may be a signal for causing the storage device 300 to enter a power saving, idle and/or sleep state. [0097]-[0098] The CPU 320 generates a control signal CTRL based on the first signal 111, i.e., the sleep mode entry signal SLEEP, and transmits the generated control signal CTRL to the PMU 330 (S120). The data storage device 300 or 300A enters a sleep mode,]
Regrading Claim 2 Jeong discloses: the I/O module (130) is further configured to cause the first interface (132) to transition from the power saving mode to the communication mode when the first interface (132) is in the power saving mode and the first signal is sent via the second interface (136). [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Regrading Claim 3 Jeong discloses: a first input configured to connect to a first field device, [includes the transmitter 231 and the receiver 232.] wherein the I/O module is further configured to derive the first process data from first field device signals received at the first input. [[0045] [0050], HSSI 230 includes the transmitter 231 and the receiver 232. For example, each of the transmitter 231 and the receiver 232 may be embodied in a structure of transmitting differential signals. The HSSI 230 may transmit or receive an instruction and/or data to or from a device side second interface (DSSI) 340 through signal lines 130-1 and 130-2 included in the second interface 130]
Regrading Claim 4 Jeong discloses: a second input configured to connect a second field device; [Fig.1 item 310] and a first output configured to connect a third field device, [receiver 312 and the transmitter 311] wherein the I/O module is further configured to derive third field device signals to be output at the first output from second field device signals received at the second input. [[0045] [0050], HSSI 230 includes the transmitter 231 and the receiver 232. For example, each of the transmitter 231 and the receiver 232 may be embodied in a structure of transmitting differential signals. The HSSI 230 may transmit or receive an instruction and/or data to or from a device side second interface (DSSI) 340 through signal lines 130-1 and 130-2 included in the second interface 130]
Regrading Claim 5 Jeong discloses: a second output configured to connect a fourth field device, [receiver 312 and the transmitter 311] wherein the I/O module is further configured to derive field device signals to be output at the second output from the second process data. . [[0045] [0050], HSSI 230 includes the transmitter 231 and the receiver 232. For example, each of the transmitter 231 and the receiver 232 may be embodied in a structure of transmitting differential signals. The HSSI 230 may transmit or receive an instruction and/or data to or from a device side second interface (DSSI) 340 through signal lines 130-1 and 130-2 included in the second interface 130]
Regrading Claim 6 Jeong discloses: the first signal comprises applying a specific voltage to a conductor connected to the second interface, and wherein receiving the second signal comprises detecting the specific voltage at the conductor connected to the second interface.[ [Fig.3 [0086] power control circuit 335B may generate each of the powers PW1, PW2, PW3, and PWn using the reference power RPW. For example, the reference power RPW may be a battery or a commercial voltage. The power control circuit 335B may control the generation timing and/or the supply timing of each of the powers PW1, PW2, PW3, and PWn using the control signal CTRL output from the CPU 320 and the values stored in the register 333.]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (Pub No. US 2015/0227187) in view of Rudaitis et al. (Pub NO. US 2020/0364166).
Regrading Claim 7 Jeong teaches : I/O module being formed according to the I/O module according to claim 1; [See rejection of claim 1 above]
Jeong does not teach a first and a second I/O module and a bus connected to the first interfaces of the first and second I/O modules;] and a conductor connected to the second interfaces of the first and second 1/O modules.
However, Rudaitis teaches: a first and a second I/O module [Fig.3, item 8, [0035] the fieldbus controller 4 may have a plurality of I/O modules 8 with a plurality of I/O connectors 6] and a bus connected to the first interfaces of the first and second I/O modules; [Fig.3, item 22, communication link 22] and a conductor connected to the second interfaces of the first and second 1/O modules. [Fig.3, Fig.5 [0038]-[0039] [0047]-[0049], a Plurality of I/O are connected to the fieldbus controller via shared communication link. A dedicated voltage-signaling conductor distinct from the main data pah, on which a first voltage level and a second voltage level are used to convey status]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to modify Jeong to include plurality of I/O module and dedicated voltage port for each I/O module as taught by Rudaitis to increase data rates and improve reliability of the system.
Regrading Claim 8 Jeong discloses: a control module configured to query the first I/O module and/or the second 1/O module for the first process data in response to the first signal. [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Regrading Claim 9 Jeong discloses: the control module is further configured to derive the second process data from the first process data and to send the second process data to the first I/O module and/or the second 1/O module. [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Regrading Claim 10 Jeong discloses: the first 1/O module and/or the second I/O module are further configured to process the second process data and, after processing, have the first interface transition from the communication mode to the power saving mode when, or as soon as, the second signal is no longer received via the second interface. [[0059] [0062] the first signal 111 may be a signal which indicates an entry into a power saving mode or a sleep state. For example, the first signal 111 may be a signal for causing the storage device 300 to enter a power saving, idle and/or sleep state. [0097]-[0098] The CPU 320 generates a control signal CTRL based on the first signal 111, i.e., the sleep mode entry signal SLEEP, and transmits the generated control signal CTRL to the PMU 330 (S120). The data storage device 300 or 300A enters a sleep mode,]
Regrading Claim 11 Jeong discloses: a higher-level control unit configured to cause the control module to transition from a sleep state to a wake state in response to an internal or external trigger mechanism, in which the control module is able to receive information from the higher-level control unit. [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Regrading Claim 12 Jeong discloses: the control module is further configured to determine, based on the information, whether the first interfaces of the first and second I/O modules are to be put into the communication mode and, if the first interfaces of the first and second I/O modules are to be put into the communication mode, to transmit the second signal to the first and second I/O modules via the conductor. [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Regrading Claim 13 Jeong discloses: a further control module, wherein the higher-level control unit is further configured to receive the information from the other control module. [[0061] The DSFI 310 may transmit the second signal 113 or WAKEUP signal, itself to the PMU 330 through a corresponding transmission line. Even if the second signal 113 or WAKEUP signal is transmitted to the CPU 320, the CPU 320 is in a power-off state. As a result, the CPU 320 may not operate in response to the second signal 113 or WAKEUP signal, and only the PMU 330 may operate in response to the second signal 113 or WAKEUP signal. Even if the CPU 320 is in a power-on state according to one or more example embodiments of the inventive concepts, the CPU 320 may not interpret the second signal 113 or WAKEUP signal. [0082]]
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Takai et al. (Patent No. US 10,218,533) teaches: interface module’s first interface with field device and transmits/output signals (process data). Wireless module’s second circuity communicates with interface module via local communication, sending/receiving signals indicating data is ready to transmit/receive. Takai also teaches set interface module out of a sleep state, wherein, when the interface module is set out of the sleep state, the interface module performs suppling of power to the field device to conduct communication with the field device.
Prior art Gao (Pub No.US 2024/0160256) teaches: When the first external device is not connected to the first interface , the pins in the first interface may be placed in a sleep state to reduce energy consumption. After putting the pins in the first interface in a sleep state, the processor may periodically detect whether the first external device is connected to the first interface based on set conditions.
Prior at Matsumoto (Pub No. US 2018/0024602) teaches: main controller performs a setting for transition to the power saving state of the first interface to the first SATA controller and performs a setting for transition to the power saving state of the second interface and the device to the second SATA controller, the first SATA controller performs the transition process on the first interface based on the setting for the transition to the power saving state performed on the first interface, the second SATA controller performs the transition process on the second interface based on the setting for the transition to the power saving state performed on the second interface, and the second SATA controller performs the transition process on the device based on the setting of the transition to the power saving state performed on the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAHID CHOUDHURY whose telephone number is (571)270-5153. The examiner can normally be reached Monday-Friday.
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175
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