DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 6, 8, 11, 13 and 14 of U.S. Patent No. 12,260,931. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 6-11, 16 and 17 are anticipated by claims. 1, 6, 8, 13 and 14 of the patent and claims 2-5, 12-15 and 18-20 would have been obvious over claims 4 and 11 of the patent.
Regarding claim 1, claim 1 of the patent recites a device, comprising:
a memory bank (claim 1, line 7); and
control circuitry (processing circuitry), configured to perform dynamic activation operations comprising:
receiving a first portion of activate information from one or more mode registers (claim 1, lines 2-7);
receiving a second portion of the activate information from an activate command (claim 1, lines 10-12); and
activating the memory bank based on the first portion of the activate information and the second portion of the activate information (claim 1, lines 8-13, the active command for activating the first memory bank comprises a first portion of activate information and a second portion of activate information).
Regarding claims 2-5, claim 4 of the patent recites the device of claim 1, wherein the first portion of the activate information comprises a number of row address terms (8 row addresses); however, claim 4 of the patent does not recite the number of the row address terms in the one or more mode registers is variable. It would have been obvious to one having ordinary skill in the art to recognize that the device of claims 2-4 and the device of claim 4 of the patent are identical in structure; therefore, the differences between claims 2-5 and claim 4 of the patent are only functional limitations.
Regarding claim 6, claim 6 of the patent recites the device of claim 1, wherein the first portion of the activate information is different from the second portion of the activate information.
Regarding claim 7, claim 1 of the patent recites the device of claim 1, wherein the one or more mode registers are selected from a plurality of mode registers.
Regarding claim 8, claim 8 of the patent recites a method comprising:
receiving, via control circuitry of a memory device, activate information (a first portion of activate information) from a mode register, wherein the memory device comprises a memory bank (claim 8, lines 2-6); and
activating the memory bank at least partially based on the activate information (claim 8, line 13).
Regarding claim 9, claim 8 of the patent recites the method of claim 8, comprising:
receiving additional activate information (a second portion of activate information) from an activate command; and
activating the memory bank at least partially based on the additional activate information (claim 8, lines 13-14).
Regarding claim 10, claim 13 of the patent recites the method of claim 9, wherein the activate information is different from the additional activate information.
Regarding claim 11, claim 14 of the patent recites the method of claim 8, comprising:
activating another memory bank at least partially based on the activate information (claim 14).
Regarding claims 12-15, claim 11 of the patent recites the method of claim 8, wherein the activate information comprises a number of row address terms (8 row addresses); however, claim 11 does not recite the number of the row address terms in the mode register is variable. It would have been obvious to one having ordinary skill in the art to recognize that the device used to perform the method of claims 12-15 and the device used to perform the method of claim 11 of the patent are identical in structure; therefore, the differences between claims 12-15 and claim 11 of the patent are only functional limitations.
Regarding claim 16, claim 8 of the patent recites the method of claim 8, wherein the mode register is selected from a plurality of mode registers.
Regarding claim 17, claim 1 of the patent recites a device, comprising:
a memory bank (a first memory bank);
processing circuitry (claim 1, lines 14-16) configured to send a first portion of activate information to one or more mode registers (claim 1, line 2-7); and
control circuitry, configured to perform dynamic activation operations comprising:
receiving the first portion of the activate information from the one or more mode registers (claim 1, lines 5-7);
receiving a second portion of the activate information from an activate command (claim 1, lines 10-12); and
activating the memory bank based on the first portion of the activate information and the second portion of the activate information (claim 1, lines 7-13).
Regarding claims 18-20. Claim 4 of the patent recites the device of claim 17, wherein the first portion of the activate information comprises a number of row address terms (8 row addresses); however, claim 4 of the patent does not recite the number of the row address terms in the one or more mode registers is variable. It would have been obvious to one having ordinary skill in the art to recognize that the device of claims 18-20 and the device of claim 4 of the patent are identical in structure; therefore, the differences between claims 8-20 and claim 4 of the patent are only functional limitations.
Claims 1, 6, 8, 10, 11 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 and 20 of U.S. Patent No. 12,073,120. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 6, 8, 10, 11 and 17 are anticipated by claims 17 and 20 of the patent.
Regarding claim 1, claim 17 of the patent recites a device (claim 17, line 5), comprising:
a memory bank (claim 17, line 5); and
control circuitry (processing circuitry), configured to perform dynamic activation operations comprising:
receiving a first portion of activate information from one or more mode registers (claim 17, lines 2-4);
receiving a second portion of the activate information from an activate command (claim 17, lines 6-10); and
activating the memory bank based on the first portion of the activate information and the second portion of the activate information (claim 17, lines 11-13).
Regarding claim 6, claim 20 of the patent recites the device of claim 1, wherein the first portion of the activate information is different from the second portion of the activate information.
Regarding claim 8, claim 17 of the patent recites a method comprising:
receiving, via control circuitry of a memory device, activate information (a first portion of activate information) from a mode register, wherein the memory device comprises a memory bank (claim 17, lines 2-4); and
activating the memory bank at least partially based on the activate information (claim 17, line 11).
Regarding claim 10, claim 20 of the patent recites the method of claim 9, wherein the activate information is different from the additional activate information.
Regarding claim 11, claim 17 of the patent recites the method of claim 8, comprising:
activating another memory bank at least partially based on the activate information (claim 17, lines 27-28).
Regarding claim 17, claim 17 of the patent recites a device (claim 17, line 5), comprising:
a memory bank (claim 17, line 5);
processing circuitry (it is inherent that there is processing circuitry to send a first portion of activate information to a mode register) configured to send a first portion of activate information to one or more mode registers; and
control circuitry, configured to perform dynamic activation operations comprising:
receiving the first portion of the activate information from the one or more mode registers (claim 17, lines 2-4);
receiving a second portion of the activate information from an activate command (claim 17, lines 6-10); and
activating the memory bank based on the first portion of the activate information and the second portion of the activate information (claim 17, lines 11-13).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hosomi (US 2001/0028114).
Regarding claim 7, Hosomi discloses a method comprising:
receiving, via control circuitry of a memory device, activate information (bank selecting signals BS1 and BS2) from a mode register (mode register 15, Fig. 15), wherein the memory device comprises a memory bank (21); and
activating the memory bank at least partially (B1) based on the activate information (paragraph [0136], lines 1-4).
Regarding claim 9, Hosomi discloses the method of claim 8, comprising:
receiving additional activate information (B2) from an activate command; and
activating the memory bank at least partially based on the additional activate information (paragraph [0136]).
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
