Detailed Action
Response to Amendment
The amendment filed on 12/18/2025 has been entered and considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al (PGPUB 2022/0020311 A1).
Independent Claims
As to claim 1, Lim (Figs. 3, 8, 9) teaches, a display apparatus (display device 10), comprising:
a display panel (pixel portion 14) configured to display an image (image IMG1)(¶ 162, 173); and
a gate driver (scan driver 13) connected to gate lines (scan lines SL1-SLm) of the display panel and configured to output a scan signal (scan signals SS1-SS4) which is to be applied to a gate line, based on a clock signal (clock signals CK1-CK4),
wherein the clock signal comprises a toggling omission time (i.e. cycles of CK1/CK3 and CK2/CK4 alternately being turned on and off in SFP1 and SFP2 as shown in Figs. 8, 9)(¶ 103, 126, 131) provided by a dividing a vertical synchronization signal time (¶ 50: i.e. interval between adjacent pulses of vertical synchronization signal is considered as the Vsync signal time. The interval of one frame based on Vsync signal is divided into a plurality of horizontal periods corresponding to Hsync as shown in Fig. 7) based on display areas (Fig. 7: i.e. single horizontal period Hsync correspond to outputting one of SS1-SS4 and driving corresponding rows of pixels. In other words, single frame based on Vsync is divided into a plurality of horizontal periods, which has a specific driving sub0areas within the entire display area).
As to claim 9, Lim (Figs. 3, 8, 9) teaches, a display apparatus (display device 10), comprising:
a display panel (pixel portion 14) configured to display an image (image IMG1)(¶ 162, 173); and
a gate driver (scan driver 13) connected to gate lines (scan lines SL1-SLm) of the display panel and configured to output a scan signal (scan signals SS1-SS4) which is to be applied to a gate lines, based on a clock signal (clock signals CK1-CK4),
wherein the clock signal comprises a toggling omission time (i.e. cycles of CK1/CK3 and CK2/CK4 alternately being turned on and off in SFP1 and SFP2 as shown in Figs. 8, 9)(¶ 103, 126, 131) provided by a dividing a vertical synchronization signal time (¶ 50: i.e. interval between adjacent pulses of vertical synchronization signal is considered as the Vsync signal time. The interval of one frame based on Vsync signal is divided into a plurality of horizontal periods corresponding to Hsync as shown in Fig. 7) based on display areas (Fig. 7: i.e. single horizontal period Hsync correspond to outputting one of SS1-SS4 and driving corresponding rows of pixels. In other words, single frame based on Vsync is divided into a plurality of horizontal periods, which has a specific driving sub0areas within the entire display area).
As to claim 13, Lim (Figs. 3, 8, 9) teaches, a gate driving circuit (scan driver 13), comprising:
a plurality of clock signal lines (clock signal lines CKL1-CKL4)(¶ 70); and
a plurality of stages (stages ST1-ST4) configured to output a scan signal (scan signals SS1-SS4), based on a clock signal (clock signals CK1-CK4) transferred through the plurality of clock signal lines (clock signals CK1-CK4),
wherein the clock signal comprises a toggling omission time (i.e. cycles of CK1/CK3 and CK2/CK4 alternately being turned on and off in SFP1 and SFP2 as shown in Figs. 8, 9)(¶ 103, 126, 131) provided by a dividing a vertical synchronization signal time (¶ 50: i.e. interval between adjacent pulses of vertical synchronization signal is considered as the Vsync signal time. The interval of one frame based on Vsync signal is divided into a plurality of horizontal periods corresponding to Hsync as shown in Fig. 7) based on display areas (Fig. 7: i.e. single horizontal period Hsync correspond to outputting one of SS1-SS4 and driving corresponding rows of pixels. In other words, single frame based on Vsync is divided into a plurality of horizontal periods, which has a specific driving sub0areas within the entire display area).
Dependent Claims
As to claims 2 and 14, Lim (Figs. 8, 9) teaches, wherein toggling of the clock signal is omitted for a time at which an output of the scan signal of an on voltage is completed (Fig. 8: i.e. during the time period when SS1 and SS3 are being applied to the gate lines, CK2 and CK4 are omitted from toggling and output as a constant logic as shown in Fig. 8 in SFP1. Similarly, Fig. 9 teaches CK1 and CK3 being omitted from toggling during SS3 and SS4 being applied during SFP2).
As to claims 3, Lim (Figs. 8, 9) teaches, wherein the clock signal is maintained in a direct current (DC) state (clocks may be maintained) for the time at which the output of the scan signal of the on voltage is completed (¶ 126, 131).
As to claim 10, Lim (Figs. 8, 9) teaches, wherein toggling omission time corresponds to a time at which an output of the scan signal of an on voltage is completed (Fig. 8: i.e. during the time period when SS1 and SS3 are being applied to the gate lines, CK2 and CK4 are omitted from toggling and output as a constant logic as shown in Fig. 8 in SFP1. Similarly, Fig. 9 teaches CK1 and CK3 being omitted from toggling during SS3 and SS4 being applied during SFP2).
As to claims 11 and 15, Lim (Figs. 8, 9) teaches, wherein the clock signal is maintained in a direct current (DC) state (clocks may be maintained) for the toggling omission time (¶ 126, 131).
As to claim 12, Lim (Figs. 8, 9) teaches, wherein the display panel comprises a first display area (i.e. odd pixel row area) and a second display area (i.e. even pixel row area) different from the first display area (Fig. 3),
first group clock signals for driving the first display area are toggled for the toggling time corresponding to a first time (first sub-frame period SFP1) of a vertical synchronization signal (vertical synchronization signal)(Figs. 3, 8: i.e. CK1 and CK3 are toggling during SFP1), and are omitted for the toggling omission time corresponding to a second time (SFP2) of the vertical synchronization signal (Fig. 9: i.e. CK1 and CK3 are maintained constant during SFP2), and second group clock signals for driving the second display area are toggled for the toggling time corresponding to the second time of the vertical synchronization signal (Figs. 3, 9: i.e. CK2 and CK4 are toggling during SFP2), and are omitted for the toggling omission time corresponding to the first time of the vertical synchronization signal (Fig. 8: i.e. CK2 and CK4 are maintained constant during SFP1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Guo et al (PGPUB 2024/0274085 A1).
As to claim 4, Lim teaches the display apparatus of claim 1, but does not specifically teach the first group of stages and the second group of stages.
Guo (Fig. 3) teaches, wherein the gate driver comprises a plurality of stages (stages GOA unit GP1-GP3000), the plurality of stages are divided into a first group of stages (GP1-GP1500) and a second group of stages (GP1501-GP3000),
the first group of stages are configured to apply scan signal to gate lines of a first display area (i.e. upper half display area) of the display panel (¶ 94, Fig. 3), and
the second group of stages are configured to apply scan signal to gate lines of a second display area (i.e. lower half display area) of the display panel (¶ 94, Fig. 3),
wherein the first group of stages are connected to first group clock signal lines (CK1-CK4)(Fig. 3), and
the second group of stages are connected to second group clock signal lines (CK1-CK4)(Fig. 3), and
wherein the first display area is different from the second display area (Fig. 3: i.e. top area vs bottom area).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Guo’s GOA circuit arrangement into Lim’s display device, so as to reduce the difference of brightnesses at different positions of the display panel (¶ 98).
As to claim 5, Lim (Fig. 3) teaches wherein the first group clock signal lines (clock lines CKL1-CKL4) comprise a first group odd clock signal line (CKL1 and CKL3) connected to a scan signal generator of an odd stage (stages ST1 and ST3) of (CKL2 and CKL4) connected to a scan signal generator (scan driver 13) of an even stage (stages ST2 and ST4)
Lim does not specifically teach the first group of stages and the second group of stages.
Guo (Fig. 3) teaches, wherein the first group clock signal lines (i.e. CK1-CK4 connected to GOA circuit 21) comprise a first group odd clock signal line (CK1 and CK2) connected to a scan signal generator (first GOA circuit 21) of an odd stage (i.e. odd stages within GOA circuit 21) of the first group of stages and a first group even clock signal line (CK3 and CK4) connected to a scan signal generator (first GOA circuit 21) of an even stage (i.e. even stages within GOA circuit 21) of the first group of stages (Fig. 3), and
the second group clock signal lines (i.e. CK1-CK4) comprise a second group odd clock signal line (CK1 and CK2) connected to a scan signal generator (second GOA circuit 22) of an odd stage (i.e. odd stages within GOA circuit 22) of the second group of stages and a second group even clock signal (CK3 and CK4) line connected to a scan signal generator (second GOA circuit 22) of an even stage (i.e. even stages within GOA circuit 22) of the second group of stages (Fig. 3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Guo’s GOA circuit arrangement into Lim’s display device, so as to reduce the difference of brightnesses at different positions of the display panel (¶ 98).
As to claim 6, Lim (Figs. 8, 9) teaches, wherein a clock signal (clock signals CK1 and CK3) applied to the first group clock signal lines is toggled for a first time (first sub-frame period SFP1) of a vertical synchronization signal (vertical synchronization signal, ¶ 50)(Fig. 8: i.e. CK1 and CK3 are toggled during SFP1), and then, is put in a direct current (DC) state for a second time (CK1 and CK3 are maintained without toggling during SFP2 in Fig. 9), and
a clock signal (clock signals CK2 and CK4) applied to the second group clock signal lines is put in a DC state (i.e. CK2 and CK4 are maintained during SFP1 as shown in Fig. 8) for the first time of the vertical synchronization signal, and then, is toggled for the second time (i.e. CK2 and CK4 are toggled during SFP2 as shown in Fig. 9).
As to claim 7, Lim (Figs. 8, 9) teaches apply a scan signal (scan signal) of an on voltage (turn-on level) to the gate lines of the first display for the first time (SFP1) of the vertical synchronization signal (¶ 50: i.e. vertical synchronization signal correspond to one frame),
apply a scan signal (scan signal) of an on voltage (turn-on level) to the gate lines of the second display for the first time (SFP2) of the vertical synchronization signal (¶ 50: i.e. vertical synchronization signal correspond to one frame).
Lim does not specifically teach the first group of stages and the second group of stages.
Guo (Fig. 3) teaches, wherein the first group of stages sequentially apply a scan signal (scan signal) of an on voltage to the gate lines of the first display area (¶ 94: i.e. sequentially supply a scan signal having a turn-on level), and
the second group of stages sequentially apply the scan signal of the on voltage to the gate lines of the second display area (¶ 94: i.e. sequentially supply a scan signal having a turn-on level).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Guo’s GOA circuit arrangement into Lim’s display device, so as to reduce the difference of brightnesses at different positions of the display panel (¶ 98).
As to claim 8, Lim teaches the display apparatus of claim 4, but does not specifically teach the first and second group of stages.
Guo (Fig. 3) teaches, wherein the first group clock signal lines and the second group clock signal lines are combined into one clock signal line (Fig. 3: i.e. the clock signals lines CK1-CK4 for first GOA circuit 21 and second GOA circuit 22 are provided by one set of CK1-CK4).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Guo’s GOA circuit arrangement into Lim’s display device, so as to reduce the difference of brightnesses at different positions of the display panel (¶ 98).
As to claim 16, Lim (Figs. 3, 8, 9) teaches, wherein the plurality of stages are divided into a first group of stages (odd stages) and a second group of stages (even stages), the plurality of clock signal lines are divided into first group clock signal lines (i.e. clock signal lines CKL1/CKL3 connected to odd stages) transmitting first group clock signals (CK1/CK3) and second group clock signal lines (i.e. clock signal lines CKL2 /CKL4 connected to even stages) transmitting second group clock signals (CK2/CK4),
wherein the first group clock signals are toggled for a first time (first sub-frame period SFP1) of a vertical synchronization signal (vertical synchronization), and then, are put in a direct current state (i.e. maintained without toggling) for a second time (SFP2)(Figs. 8, 9: i.e. CK1 and CK3 toggling in SFP1 and stay maintained in SFP2), and
wherein the second group clock signals are put in a DC state (i.e. maintained without toggling) for the first time of the vertical synchronization signal, and then, are toggled for the second time (Figs. 8, 9: i.e. CK2 and CK4 maintained in SFP1 and toggling in SFP2).
Lim does not specifically teach the first group and second group of stages.
Guo (Fig. 3) teaches, wherein the first group of stages (stage GOA unit GP1-GP1500) are connected to the first group clock signal lines (CK1-CK4)(Fig. 3),
wherein the second group of stages (stage GOA unit 1501-3000) are connected to the second group clock signal lines (CK1-CK4)(Fig. 3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Guo’s GOA circuit arrangement into Lim’s display device, so as to reduce the difference of brightnesses at different positions of the display panel (¶ 98).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of In (PGPUB 2022/0028323 A1).
As to claim 17, Lim teaches the display apparatus of claim 1 but does not specifically teach clock signal toggles multiple times during a time when an ON voltage of the scan signal is output.
In (Fig. 4) teaches, wherein during a time when an on volage of the scan signal is output, the clock signal toggles multiple times (Fig. 4: i.e. clock signal CLK2 toggles from L to H to L to H during time periods t2-t6. During this time period, output signal OUT1 is at high level H or intermediate level M).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate In’s scan driver driving method into Lim’s display driving circuit, so as to improve image quality in stable high speed driving (¶ 209).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim in view of Jung et al (PGPUB 2020/0203382 A1).
As to claim 18, Lim (Fig. 3) teaches the gate driver comprises a plurality of stages (Fig. 3).
Jung does not specifically teach wherein each of the plurality of stages is configured to receive a single clock signal rather than multiple clock signals.
Jung (Fig. 8) teaches, wherein each of the plurality of stages is configured to receive a single clock signal (clock signal CLK) rather than multiple clock signals (¶ 77, Fig. 8)
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Jung’s driving method into Lim’s display device, so as to implement multi-display device (¶ 241).
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Applicant has amended claims 1, 9 and 13 to recite the new limitation, “wherein the clock signal comprise a toggling omission time provided by dividing a vertical synchronization signal time based on display areas”. Applicant further argues that Lim prior art does not specifically teach this limitation. Examiner respectfully disagrees. On ¶ 50, Lim defines interval between adjacent pulses of the vertical synchronization signal corresponds to one frame. The interval is equivalent to the vertical synchronizing signal time in the claim. As shown in Figs. 5 and 6, one frame period FP1 is divided into multiple horizonal periods defined by Hsync signal. Each Hsync signal corresponds to driving period of corresponding row of pixels. In the case of the embodiment in Fig. 7, each horizontal period correspond to each of scan signals SS1-SS4. In other words, each turning on / off timing of clock signals CK1-CK4 are provided by each respective horizontal period, which is a division of the interval, and generated based on specific row of corresponding pixels for SS1-SS4. Therefore, Lim prior art still teaches the limitations discussed in the new amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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