DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “orthogonal projection,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 10-13 and 16 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abhyankar et al. (hereinafter Abhyankar) (US9298228).
Regarding claim 1, Abhyankar discloses a server (server, Col 2, Line 51), comprising:
a mainboard (motherboard 10, Col; Line 53) comprising memory expansion connectors (DIMM connectors 162, 163, 662 and 663, Col 3, Line 15);
a central processing unit (CPU) (CPU, Co; 2, line 53) on the mainboard (10) and coupled (Figure 1) to the memory expansion connectors (162, 163, 662 and 663); and
an expanded memory module group (riser cards 120 and 620, mezzanine cards 130 and 630 and several dual inline memory modules (DIMMa) 140, 142, 144, 640, 642, 644, Col2, Line 54) located on one side (Figure 1) of the mainboard (10) and spaced from the mainboard (10), wherein the expanded memory module group (riser cards 120 and 620, mezzanine cards 130 and 630 and several dual inline memory modules (DIMMa) 140, 142, 144, 640, 642, 644, Col2, Line 54) is coupled to the memory expansion connectors (162, 163, 662 and 663).
Regarding claim 2, Abhyankar discloses the server according to claim 1, wherein the expanded memory module group comprises a plurality of expanded memory units independently arranged, and each expanded memory unit is coupled to one or more of the memory expansion connectors. (Figure 1)
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Regarding claim 3, Abhyankar discloses the server according to claim 2, wherein each expanded memory unit comprises a circuit board, and a plurality of circuit boards of different expanded memory units are spaced apart from each other. (aforementioned Figure 1)
Regarding claim 4, Abhyankar discloses the server according to claim 2, wherein each expanded memory unit comprises a circuit board, and a plurality of circuit boards of different expanded memory units are interconnected to form an integrated structure. (aforementioned Figure 1)
Regarding claim 7, Abhyankar discloses the server according to claim 1, further comprising: a housing enclosing an accommodation cavity, wherein the mainboard is in the accommodation cavity; and a bracket connected to the housing wherein the bracket is located on one side of the mainboard and spaced from the mainboard; and the expanded memory module group is arranged on the bracket. (Figure 9A)
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Regarding claim 10, Abhyankar discloses an electronic device, comprising:
a power supply unit (PSU) (418); and
a server (Column 9, Lines 53-59) coupled to the PSU (418), wherein the server comprises (Column 9, Lines 53-59):
a mainboard (motherboard 10, Col; Line 53) comprising memory expansion connectors (DIMM connectors 162, 163, 662 and 663, Col 3, Line 15);
a central processing unit (CPU) (CPU, Co; 2, line 53) on the mainboard (10) and coupled (Figure 1) to the memory expansion connectors (162, 163, 662 and 663); and
an expanded memory module group (riser cards 120 and 620, mezzanine cards 130 and 630 and several dual inline memory modules (DIMMa) 140, 142, 144, 640, 642, 644, Col2, Line 54) located on one side (Figure 1) of the mainboard (10) and spaced from the mainboard (10), wherein the expanded memory module group (riser cards 120 and 620, mezzanine cards 130 and 630 and several dual inline memory modules (DIMMa) 140, 142, 144, 640, 642, 644, Col2, Line 54) is coupled to the memory expansion connectors (162, 163, 662 and 663).
Regarding claim 11, Abhyankar discloses the electronic device according to claim 10, wherein the expanded memory module group comprises a plurality of expanded memory units independently arranged, and each expanded memory unit is coupled to one or more of the memory expansion connectors. (aforementioned Figure 1)
Regarding claim 12, Abhyankar discloses the electronic device according to claim 11, wherein each expanded memory unit comprises a circuit board, and a plurality of circuit boards of different expanded memory units are spaced apart from each other. (aforementioned Figure 1)
Regarding claim 13, Abhyankar discloses the electronic device according to claim 11, wherein each expanded memory unit comprises a circuit board, and a plurality of circuit boards of different expanded memory units are interconnected to form an integrated structure. (aforementioned Figure 1)
Regarding claim 16, Abhyankar discloses the electronic device according to claim 10, further comprising: a housing enclosing an accommodation cavity, wherein the mainboard is in the accommodation cavity; and a bracket connected to the housing, wherein the bracket is located on one side of the mainboard and spaced from the mainboard, and the expanded memory module group is arranged on the bracket. (aforementioned figure 9A)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5, 6, 12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abhyankar et al. (hereinafter Abhyankar) (US9298228) in view of Norton et al. (hereinafter Norton) (US20210315124).
Regarding claim 5, Abhyankar discloses the server according to claim 1.
Abhyankar does not expressly disclose wherein the server comprises a first cable that supports a cache-coherent bus, and an expanded memory unit comprises: a first high-speed connector coupled to the memory expansion connectors via the first cable; and memory media coupled to the first high-speed connector.
Norton discloses a first cable that supports a cache-coherent bus, and an expanded memory unit comprises: a first high-speed connector coupled to the memory expansion connectors via the first cable; and memory media coupled to the first high-speed connector (Paragraph 0053 – in its entirety).
It would’ve been obvious to one of ordinary skill in the art, before the effective filing date of the invention to incorporate the cable supported cache-coherent bus of Norton into the server of Abhyankar.
One having ordinary skill on the art would have been motivated to do this to incorporate functionality, including, but not limited to, memory coherency, memory management, and/or memory allocation.
Regarding claim 6, Abhyankar in view of Norton, discloses the server according to claim 5, wherein the expanded memory unit further comprises: a memory expansion controller serially coupled between the first high-speed connector and the memory media; and a plurality of memory media coupled to the memory expansion controller comprising one or more types of memory media. (aforementioned Paragraph 0053 – Norton)
Regarding claim 12, Abhyankar discloses the electronic device according to claim 10
Abhyankar does not expressly disclose wherein the server comprises a first cable that supports a cache-coherent bus, and an expanded memory unit comprises: a first high-speed connector coupled to the memory expansion connectors via the first cable; and memory media coupled to the first high-speed connector.
Norton et al. (hereinafter Norton) (US20210315124) discloses a first cable that supports a cache-coherent bus, and an expanded memory unit comprises: a first high-speed connector coupled to the memory expansion connectors via the first cable; and memory media coupled to the first high-speed connector (Paragraph 0053 – in its entirety).
It would’ve been obvious to one of ordinary skill in the art, before the effective filing date of the invention to incorporate the cable supported cache-coherent bus of Norton into the server of Abhyankar.
One having ordinary skill on the art would have been motivated to do this to incorporate functionality, including, but not limited to, memory coherency, memory management, and/or memory allocation.
Regarding claim 15, Abhyankar, in view of Norton discloses the electronic device according to claim 14, wherein the expanded memory unit further comprises:
a memory expansion controller serially coupled between the first high-speed connector and the memory media; and a plurality of memory media coupled to the memory expansion controller comprising one or more types of memory media. (aforementioned Paragraph 0053 – Norton)
Allowable Subject Matter
Claims 8, 9, 17 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, the prior art of record, taken alone or in combination, fails to teach or suggest the interconnection and interrelationship wherein the extended memory module group and the CPU are on a same side of the mainboard; and an orthogonal projection of the expanded memory module group on the mainboard at least partially overlaps with an orthogonal projection of the CPU on the mainboard, as claimed with the remaining limitations of independent claim 1.
Regarding claim 9, the prior art of record, taken alone or in combination, fails to teach or suggest the interconnection and interrelationship of a memory module group located on the mainboard and spaced from the CPU; and an orthogonal projection of the expanded memory module group on the mainboard at least partially overlapping with an orthogonal projection of the memory module group on the mainboard, as claimed with the remaining limitations of independent claim 1.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or suggest the interconnection and interrelationship wherein the extended memory module group and the CPU are on a same side of the mainboard; and an orthogonal projection of the expanded memory module group on the mainboard at least partially overlaps with an orthogonal projection of the CPU on the mainboard, as claimed with the remaining limitations of independent claim 10.
Regarding claim 18, the prior art of record, taken alone or in combination, fails to teach or suggest the interconnection and interrelationship of a memory module group located on the mainboard and spaced from the CPU; and an orthogonal projection of the expanded memory module group on the mainboard at least partially overlapping with an orthogonal projection of the memory module group on the mainboard, as claimed with the remaining limitations of independent claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US11419239, US10694635.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Xanthia C Cunningham whose telephone number is (571)270-1963. The examiner can normally be reached Tuesday -Friday 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani Hayman can be reached on 571-270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XANTHIA C RELFORD/ Primary Examiner, Art Unit 2841
7 October 2026
