DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/16/2026 has/have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al (CN 117615124 A), hereinafter Cai.
-Regarding claim 1, Cai discloses a system-on-chip-based image processing method, comprising (Abstract; FIGS. 1-10; Page 11, 2nd paragraph; Page 19, last paragraph – Page 20, 2nd paragraph): determining abnormal information generated during processing a first image data frame by a plurality of image processing modules in the system-on-chip and path configuration information corresponding to the plurality of image processing modules (FIG. 2, S10; FIGS. 1, 3-10; Page 3, 3rd – 4th paragraphs; Page 8, 3rd paragraph); determining an abnormal module that generates the abnormal information and an initial handling strategy used to address the abnormal information (FIG. 10, S20; FIGS. 1-9; Page 8, 4th – 6th paragraphs; Page 5, 3rd – 5th paragraphs); determining a target to-be-processed module from the plurality of image processing modules based on the abnormal module, the initial handling strategy, and the path configuration information (FIG. 2, S10-S20; FIG. 4, S12-S20; FIG. 5, S21-S23; FIG. 10, S30; ; FIGS. 1, 3, 6-9; Page 4, 1st – 11th paragraph; Page 14, 5th – 7th paragraphs); processing the target to-be-processed module based on the initial handling strategy (FIG. 2, S30; FIG. 10, S30; FIGS. 1, 3-9); and continuing to process a second image data frame by using the processed target to-be-processed module (FIG. 8).
-Regarding claim 2, Cai discloses the method of claim 1. Cai further discloses analyzing the abnormal information to determine the abnormal module, and a module identifier and/or an abnormality type of the abnormal module; and searching for an abnormality handling correspondence based on the abnormal module, the module identifier, and/or the abnormality type, to determine a handling strategy corresponding to the abnormal module, the module identifier, and/or the abnormality type as the initial handling strategy (FIG. 4, S12; FIG. 6; FIG. 8, identifier: input frame rate, fault count time; abnormality type: abnormality to be fixed by camera soft reset, camera hard restart, or SOC power down; FIG. 10).
-Regarding claim 8, Cai discloses the method of claim 1. Cai further discloses determining the plurality of image processing modules as the target to-be-processed module in response to that the initial handling strategy is system reset (FIG. 6, 8, 10).
-Regarding claim 18, Cai discloses the method of claim 1. Cai further discloses determining a quantity of times for which the abnormal module generates the abnormal information during a preset time period; and in response to that the quantity of times is greater than or equal to a threshold of times, processing the target to-be-processed module based on a preset handling strategy to obtain the processed target to-be-processed module, wherein the preset handling strategy is a valid strategy for eliminating the abnormal information (FIG. 8; FIGS. 4, 6, 10).
-Regarding claim 19, Cai discloses a non-transitory computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a system-on- chip-based image processing method (FIGS. 1, 3, 7; Page 5, 6th paragraph), wherein the method comprises (Abstract; FIGS. 1-10; Page 11, 2nd paragraph; Page 19, last paragraph – Page 20, 2nd paragraph): determining abnormal information generated during processing a first image data frame by a plurality of image processing modules in the system-on-chip and path configuration information corresponding to the plurality of image processing modules (FIG. 2, S10; FIGS. 1, 3-10; Page 3, 3rd – 4th paragraphs; Page 8, 3rd paragraph); determining an abnormal module that generates the abnormal information and an initial handling strategy used to address the abnormal information (FIG. 10, S20; FIGS. 1-9; Page 8, 4th – 6th paragraphs; Page 5, 3rd – 5th paragraphs); determining a target to-be-processed module from the plurality of image processing modules based on the abnormal module, the initial handling strategy, and the path configuration information (FIG. 2, S10-S20; FIG. 4, S12-S20; FIG. 5, S21-S23; FIG. 10, S30; ; FIGS. 1, 3, 6-9; Page 4, 1st – 11th paragraph; Page 14, 5th – 7th paragraphs); processing the target to-be-processed module based on the initial handling strategy (FIG. 2, S30; FIG. 10, S30; FIGS. 1, 3-9); and continuing to process a second image data frame by using the processed target to-be-processed module (FIG. 8).
-Regarding claim 20, Cai discloses an electronic device, wherein the electronic device comprises: a processor; and a memory, configured to store processor-executable instructions, wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a system-on-chip-based image processing method (FIGS. 1, 3, 7; Page 5, 6th paragraph), wherein the method comprises (Abstract; FIGS. 1-10; Page 11, 2nd paragraph; Page 19, last paragraph – Page 20, 2nd paragraph): determining abnormal information generated during processing a first image data frame by a plurality of image processing modules in the system-on-chip and path configuration information corresponding to the plurality of image processing modules (FIG. 2, S10; FIGS. 1, 3-10; Page 3, 3rd – 4th paragraphs; Page 8, 3rd paragraph); determining an abnormal module that generates the abnormal information and an initial handling strategy used to address the abnormal information (FIG. 10, S20; FIGS. 1-9; Page 8, 4th – 6th paragraphs; Page 5, 3rd – 5th paragraphs); determining a target to-be-processed module from the plurality of image processing modules based on the abnormal module, the initial handling strategy, and the path configuration information (FIG. 2, S10-S20; FIG. 4, S12-S20; FIG. 5, S21-S23; FIG. 10, S30; ; FIGS. 1, 3, 6-9; Page 4, 1st – 11th paragraph; Page 14, 5th – 7th paragraphs); processing the target to-be-processed module based on the initial handling strategy (FIG. 2, S30; FIG. 10, S30; FIGS. 1, 3-9); and continuing to process a second image data frame by using the processed target to-be-processed module (FIG. 8).
Allowable Subject Matter
Claims 3-7 and 9-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han et al (A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No.12 2016), hereinafter Han teaches a fault-tolerant cache system of automotive vision processors with fault analysis complying with ISO26262. The fault-tolerant cache system recovers the memory when errors are not corrected by ECC and reconfigures to the size of tag/data memory to prevent the errors by a prediction and reduce the error trap rate of the processor.
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/XIAO LIU/Primary Examiner, Art Unit 2664
