DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
Examiner states for the record that no Information Disclosure Statement is presently filed in this application.
Election/Restrictions
Applicant’s election without traverse of claims 9-15 and 23-25 of Group II in the reply filed on May 28, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 10, 23, 24, 30, and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (Pub. No. US 2004/0117441).
Claim 9:
Liu et al. disclose a memory system, comprising:
one or more memory devices [figs. 1-3; par. 0037-0038 – “Storage 125 includes any computer-readable media which stores data. Computer storage media can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can store the information and that can be accessed by a computing device. Most commonly, storage 125 will be some sort of mass storage device, such as one or more hard disk drives.”]; and
processing circuitry coupled with the one or more memory devices [figs. 1-3; pars. 0009, 0030-0036 – “FIG. 1 is a block diagram representing an exemplary environment in which the invention may be practiced in accordance with some aspects of the invention. The environment includes server 105, fabric 115, data-aware data flow manager 120 and storage 125. The devices shown in the environment are interconnected by a network having communication links. In some embodiments of the invention, data-aware data flow manager 120 is incorporated in server 105, fabric 115, or storage 125. In other embodiments of the invention, data-aware data flow manager 120 and storage 125 are incorporated in server 105. Data-aware data flow manager 120 may be incorporated at multiple places within the environment. For example, data-aware data flow manager 120 may be incorporated on server 105 or storage 125 in addition to, or alternatively from, being inserted between fabric 115 and storage 125.” … “Data-aware data flow manager 120 is a device or process that intelligently caches or does not cache data, depending on a variety of factors which are described in more detail below. Briefly, when data-aware data flow manager 120 receives data that needs to be written to storage 125 or data that has been retrieved from storage 125, data-aware data flow manager 120 may decide to cache the data or send the data through without caching the data.”] and configured to cause the memory system to:
generate a first read command associated with accessing a set of memory cells of a memory device of the one or more memory devices [pars. 0009, 0063-0069 – “Similarly, the data-aware data flow manager may read more data from storage than was requested by a server. The extra data may be cached in a memory of the data-aware data flow manager in anticipation of future read requests from the server.” … “One or more policies may affect what data is cached and under what conditions. For example, a policy may indicate there should be no write-back caching, that only reads should be cached and not writes, or that only writes should be cached and not reads. A policy may indicate that a certain volume should have a cache equal or greater in size than the volume. This may allow, for example, the data in the volume to be completely stored in the cache. A policy may indicate that intelligent data flow manager 430 should not cache data written to a certain LUN. A policy may indicate that when the stress of a cache exceeds a certain threshold, that the cache should be bypassed for certain types of data accesses (e.g., large reads or writes).”];
determine, based at least in part on generating the first read command, whether a size of the first read command satisfies a first threshold and whether a remaining size of a data transfer unit satisfies a second threshold [pars. 0063-0069, 0080; claim 21 – Data is selectively cached according to the size of the read and the stress of the cache (i.e. free lines in the cache). A free cache line satisfies a remaining size threshold. (“A policy may indicate that when the stress of a cache exceeds a certain threshold, that the cache should be bypassed for certain types of data accesses (e.g., large reads or writes).” … “Data-aware cache 405 may inform intelligent data flow manager 430 of data-aware cache 405's stress. Stress may include how much cache is free, if the data-aware cache 405 has enough cache free to service the request, or the extent to which the cache is dirty.” … “The computer-readable medium of claim 15, wherein determining whether to cache the data comprises applying a policy that indicates that the cache should be bypassed for reads or writes exceeding a certain size.”)]; and
transmit the data transfer unit, or the data transfer unit and a second data transfer unit, based at least in part on determining whether the size of the first read command satisfies the first threshold and whether the remaining size of the data transfer unit satisfies the second threshold [par. 0079, 0108 – Cache lines according to the read are returned based on the prior determination and also a determination that the data is present in the cache. (“Data-aware cache 405 may indicate information regarding hit/miss performance of the cache including whether the request generates a hit, partial hit, or miss. A partial hit occurs when some but not all of the data that is requested to be read or written is contained within the cache. For example, a server may request a number of blocks of data. Part of the data may be found in data-aware cache 405, while another part of the data might not exist in data-aware cache 405. Upon receipt of this information, intelligent data flow manager 430 may forward the information (or a pointer thereto) to system stats manager 415 which may then update its statistics. Intelligent data flow manager 430 may also forward other information to system stats manager 415 including size of read or write, associated LUN or LUNs, and the like.” … “For example, if the cache is under stress and dirty lines have to be flushed before freeing up cache lines for the read request (e.g., read induced write and read wait on write), then bypassing cache may shorten the latency and the response time to the read request. At block 755, a data pointer (or a set of data pointers in a scatter gather list) is set to point to one or more free cache lines that have been assigned to receive the data from the read request.”)].
Claim 10 (as applied to claim 9 above):
Liu et al. disclose, wherein the processing circuitry is further configured to cause the memory system to:
transmit the data transfer unit based at least in part on determining that the size of the first read command satisfies the first threshold and that the remaining size of the data transfer unit satisfies the second threshold [par. 0079, 0108 – Cache lines according to the read are returned based on the prior determination and also a determination that the data is present in the cache. (“Data-aware cache 405 may indicate information regarding hit/miss performance of the cache including whether the request generates a hit, partial hit, or miss. A partial hit occurs when some but not all of the data that is requested to be read or written is contained within the cache. For example, a server may request a number of blocks of data. Part of the data may be found in data-aware cache 405, while another part of the data might not exist in data-aware cache 405. Upon receipt of this information, intelligent data flow manager 430 may forward the information (or a pointer thereto) to system stats manager 415 which may then update its statistics. Intelligent data flow manager 430 may also forward other information to system stats manager 415 including size of read or write, associated LUN or LUNs, and the like.” … “For example, if the cache is under stress and dirty lines have to be flushed before freeing up cache lines for the read request (e.g., read induced write and read wait on write), then bypassing cache may shorten the latency and the response time to the read request. At block 755, a data pointer (or a set of data pointers in a scatter gather list) is set to point to one or more free cache lines that have been assigned to receive the data from the read request.”)].
Claim 23:
Claim 23, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 9 above, mutatis mutandis.
Claim 24 (as applied to claim 23 above):
Claim 24, directed to a method, is rejected for the same reasons set forth in the rejection of claim 10 above, mutatis mutandis.
Claim 30:
Claim 30, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 9 above, mutatis mutandis.
Claim 31 (as applied to claim 30 above):
Claim 312, directed to method, is rejected for the same reasons set forth in the rejection of claim 10 above, mutatis mutandis.
Allowable Subject Matter
Claims 11-15, 25-29, and 32-35 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
25 July 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
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