DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 & 7-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (US 20130083449) (commonly owned).
In regards to claim 1, Yoon ‘449 discloses
A multilayer ceramic capacitor, comprising
a capacitor body including a dielectric layer (111 – fig. 2; [0035]) and an internal electrode layer (130a/130b – fig. 2; [0035]), and
an external electrode (120a/120b – fig. 2; [0035])disposed on an outer surface of the capacitor body,
wherein the dielectric layer includes a barium titanate-based main component ([0048] & table 3 – sample 27) and a subcomponent including cerium (Ce) and dysprosium (Dy) ([0061-0062] & table 3 – sample 27), and
a Ce/Dy molar ratio is 1 to 10 (table 3 – sample 27).
In regards to claim 2, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 1, wherein the dielectric layer includes a plurality of dielectric grains ([0054]).
In regards to claim 3, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 2, wherein the dielectric layer includes a first plurality of dielectric layers and a second plurality of dielectric layers (fig. 2),
the internal electrode layer includes a plurality of internal electrode layers (fig. 2; [0006]),
the capacitor body includes:
an active region that includes the first plurality of dielectric layers and the plurality of the internal electrode layers alternately arranged (fig. 2; [0075]), and
a cover region that includes the second plurality of dielectric layers disposed on surfaces of the active region opposing each other in a thickness direction (fig. 2),
wherein the active region includes an active center defined as a region from an exact center of the active region to a region where two dielectric layers, among the first plurality of dielectric layers, along the thickness direction, and adjacent to the center of the active region, are visible, and an active end defined as a region from a boundary between the active region and the cover region to a region where four dielectric layers among the first plurality of dielectric layers are visible (fig. 2), and
when an average size of the plurality of dielectric grains at the active center is D1 and the average size of the plurality of dielectric grains at the active end is D2, a dielectric grain size deviation rate obtained from Equation 1 is greater than or equal to 0% and less than 10%:
[Equation 1]
Dielectric grain size deviation rate (%) = (|D1-D2|/D1) x 100
wherein a size of the plurality of dielectric grains is an average value of a major axis length and a minor axis length of the plurality of dielectric grains (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Dielectric grain size deviation rate) are presumed to be inherent.
In regards to claim 4, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 3, wherein when the dielectric grain size deviation rate is greater than 0% and less than 10%, D1 has a value greater than D2 (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Dielectric grain size deviation rate) are presumed to be inherent.
In regards to claim 7, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 1, wherein cerium (Ce) is included in an amount of 1 part by mole to 2 parts by mole based on 100 parts by mole of the barium titanate-based main component (table 3 – sample 27).
In regards to claim 8, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 1, wherein dysprosium (Dy) is included in an amount of 0.2 parts by mole to 1 part by mole based on 100 parts by mole of the barium titanate-based main component (table 3 – sample 27).
In regards to claim 9, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 1, wherein a capacitance variation coefficient ratio, as calculated by Equation 2, of the multilayer ceramic capacitor is greater than 0% and less than 3%:
[Equation 2]
Capacitance variation coefficient ratio (Cp CV) (%) = {capacitance standard deviation (σ1)/ capacitance mean} X 100
wherein, in Equation 2, capacitance standard deviation (σ1) is a square root of an average of squares of capacitance deviations (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Capacitance variation coefficient ratio) are presumed to be inherent.
In regards to claim 10, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 1, wherein a dielectric loss variation coefficient ratio, as calculated by Equation 3, of the multilayer ceramic capacitor is greater than 0% and less than 6%:
[Equation 3]
Dielectric loss variation coefficient ratio (DF CV) (%) = {dielectric loss standard deviation (σ2)/ dielectric loss mean} X 100
wherein, in Equation 3, dielectric loss standard deviation (σ2) is a square root of an average of squares of dielectric loss deviations (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Dielectric loss variation coefficient ratio) are presumed to be inherent.
In regards to claim 11, Yoon ‘449 discloses
A method of manufacturing a multilayer ceramic capacitor, comprising
mixing barium titanate-based main component powder ([0048]) and subcomponent powder to prepare a dielectric slurry ([0072]);
manufacturing a plurality of dielectric green sheets from the dielectric slurry and forming a conductive paste layer on a surface of each dielectric green sheet among the plurality of dielectric green sheets ([0074-0075]);
manufacturing a dielectric green sheet stack by stacking the plurality of dielectric green sheets on which the conductive paste layer is formed ([0075]);
manufacturing a capacitor body including a dielectric layer and an internal electrode layer by firing the dielectric green sheet stack ([0076]); and
forming an external electrode on one surface of the capacitor body ([0075]),
wherein the dielectric layer includes a barium titanate-based main component ([0048] & table 3 – sample 27) and a subcomponent including cerium (Ce) and dysprosium (Dy) ([0061-0062] & table 3 – sample 27),
the subcomponent powder includes a Ce-containing compound and a Dy- containing compound, and the Ce-containing compound and the Dy-containing compound are included in an amount such that a Ce/Dy molar ratio is 1 to 10 (table 3 – sample 27).
In regards to claim 12, Yoon ‘449 discloses
The method of claim 11, wherein the Ce-containing compound is included in an amount such that Ce is 1 part by mole to 2 parts by mole based on 100 parts by mole of the barium titanate- based main component (table 3 – sample 27).
In regards to claim 13, Yoon ‘449 discloses
The method of claim 11, wherein the Dy-containing compound is included in an amount such that Dy is 0.2 parts by mole to 1 part by mole based on 100 parts by mole of the barium titanate- based main component (table 3 – sample 27).
In regards to claim 14, Yoon ‘449 discloses
The method of claim 11, wherein the Ce-containing compound and the Dy-containing compound each include an oxide, a nitride, or a salt compound, or the Ce-containing compound and the Dy-containing compound each includes a sol form dispersed in an organic solvent (table 3 – sample 27 & [0072]).
In regards to claim 15, Yoon ‘449 discloses
The method of claim 11, wherein the Ce-containing compound includes CeO2, and the Dy-containing compound includes Dy2O3 (table 3 – sample 27).
In regards to claim 16, Yoon ‘449 discloses
A multilayer ceramic capacitor, comprising
a capacitor body including a dielectric layer (111 – fig. 2; [0035]) and an internal electrode layer (130a/130b – fig. 2; [0035]), the dielectric layer including cerium (Ce) and dysprosium (Dy), wherein a Ce/Dy molar ratio is 1 to 10 (table 3 – sample 27), and
an external electrode (1320a/120b – fig. 2; [0035]) disposed on an outer surface of the capacitor body.
In regards to claim 17, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 16, wherein the dielectric layer includes a plurality of dielectric grains([0054]).
In regards to claim 18, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 17, wherein the dielectric layer includes
a first plurality of dielectric layers and a second plurality of dielectric layers (fig. 2),
the internal electrode layer includes a plurality of internal electrode layers (fig. 2; [0006]),
the capacitor body includes:
an active region that includes the first plurality of dielectric layers and the plurality of the internal electrode layers alternately arranged (fig. 2; [0075]), and
a cover region that includes the second plurality of dielectric layers disposed on surfaces of the active region opposing each other in a thickness direction (fig. 2),
wherein the active region includes an active center defined as a region from an exact center of the active region to a region where two dielectric layers, among the first plurality of dielectric layers, along the thickness direction, and adjacent to the center of the active region, are visible, and an active end defined as a region from a boundary between the active region and the cover region to a region where four dielectric layers among the first plurality of dielectric layers are visible (fig. 2), and
when an average size of the plurality of dielectric grains at the active center is D1 and the average size of the plurality of dielectric grains at the active end is D2, a dielectric grain size deviation rate obtained from Equation 1 is greater than or equal to 0% and less than 10%:
[Equation 1]
Dielectric grain size deviation rate (%) = (|D1-D2|/D1) x 100
wherein a size of the plurality of dielectric grains is an average value of a major axis length and a minor axis length of the plurality of dielectric grains (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Dielectric grain size deviation rate) are presumed to be inherent.
In regards to claim 19, Yoon ‘449 discloses
The multilayer ceramic capacitor of claim 18, wherein when the dielectric grain size deviation rate is greater than 0% and less than 10%, D1 has a value greater than D2 (table 3 – sample 27 – based on the composition of the ceramic specifically the Ce/Dy ratio said limitation is met). When the structure recited in the references is substantially identical to that of the claims, claimed properties (Dielectric grain size deviation rate) are presumed to be inherent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-6 & 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon ‘449 in view of KR102067003 hereafter referred to as Lee.
In regards to claim 5/20,
Yoon ‘449 fails to disclose wherein D1 is 210 nm to 230 nm.
Lee discloses wherein ceramic layer has dielectric grains with a particle size of 210 nm to 230 nm ([0088-0090], [0150] & table 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form D1 of Yoon ‘449 to be a value as taught by Lee to obtain a capacitor wherein dielectric strength characteristics are improved and breakdown voltage and accelerated life degradation can be prevented. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 6/21,
Yoon ‘449 fails to disclose wherein D2 is 200 nm to 220 nm.
Lee discloses wherein ceramic layer has dielectric grains with a particle size of 200 nm to 220 nm ([0088-0090], [0150] & table 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form D2 of Yoon ‘449 to be a value as taught by Lee to obtain a capacitor wherein dielectric strength characteristics are improved and breakdown voltage and accelerated life degradation can be prevented. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0411246 – [0112] US 2013/0250478 – table 1
US 2025/0279244 – [0048] KR1020190012240A – table 3
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
