DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/13/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 18-20 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Manganelli et al. (US 2021/0335432).
Consider claim 1, Mangenelli et al. discloses a memory system, comprising: a memory controller; and a memory device coupled to the memory controller, the memory device comprising a plurality of memory regions; wherein the memory controller is configured to: perform a redundant array coding operation on user data to generate check data (abstract, [0036], [0040], [0042], [0070], [0098], Mangenelli et al. discloses a memory device with a plurality of regions in the form of pages, sub-blocks, blocks planes and SLC/MLC type regions. Redundant array coding is also disclosed that uses parity information.); allocate a first physical address for storing the user data; wherein the first physical address points to a first memory region of the plurality of memory regions; allocate a second physical address for storing the check data, and recording the second physical address; wherein the second physical address points to a second memory region of the plurality of memory regions that is different from the first memory region (abstract, [0013], [0044], [0080], [0083], [0098], [0100], Mangenelli et al. discloses storing user data in a first region with MLC memory storage and parity data in a second region with SLC memory storage.); send a first writing instruction comprising the first physical address to the memory device, wherein the first writing instruction indicates to write the user data into the first memory region; and send a second writing instruction that comprises the second physical address and is different from the first writing instruction to the memory device; wherein the second writing instruction indicates to write the check data into the second memory region (abstract, [0013], [0044], [0080], [0083], [0098], [0100], Mangenelli et al. discloses storing user data in a first region with MLC memory storage and parity data in a second region with SLC memory storage. The Schema controller determines where to write both user and parity data.).
Consider claim 2, Mangenelli et al. discloses the memory system according to claim 1, wherein the first memory region comprises a plurality of first dies, and the first die comprises a plurality of first memory blocks; wherein a plurality of the first memory blocks in different first dies form a superblock; wherein the memory controller is configured to: allocate the first physical address based on the plurality of managed superblocks, wherein the first physical address points to a target superblock in a plurality of superblocks (abstract, [0013], [0036], [0042], [0044], [0070], [0071], [0080], [0083], [0098], [0100], Mangenelli et al. discloses an MLC first memory region where data is striped across page lines and planes (superblock).).
Consider claim 3, Mangenelli et al. discloses the memory system according to claim 2, wherein the second memory region comprises at least one second die, the second die comprises a plurality of second memory blocks; wherein the memory controller is further configured to: allocate the second physical address based on a plurality of managed second memory blocks, wherein the second physical address points to a target second memory block in the plurality of the second memory blocks (abstract, [0013], [0036], [0042], [0044], [0070], [0071], [0080], [0083], [0098], [0100], Mangenelli et al. discloses an SLC memory region with blocks for storing parity data.).
Consider claim 4, Mangenelli et al. discloses the memory system according to claim 2, wherein the memory controller is further configured to: obtain a first metadata related to the user data from the memory device, wherein the first metadata comprises index information related to the check data; and retrieve a mapping table based on the index information to determine the second physical address for storing the check data, wherein the mapping table comprises a mapping relationship between the index information and the second physical address (abstract, [0013], [0044], [0080], [0083], [0098], [0100], Mangenelli et al. discloses storing user data in a first region with MLC memory storage and parity data in a second region with SLC memory storage. The Schema controller determines where to write both user and parity data. Parity data’s location is known and used to determine which parity data is related to which user data.).
Consider claim 5, Mangenelli et al. discloses the memory system according to claim 4, wherein the mapping table comprises a plurality of entries, and one of the entries records the second physical address corresponding to one piece of the index information; and the memory controller is configured to: retrieve the mapping table based on the index information to determine a target entry in the plurality of entries; and determine the second physical address for storing the check data based on the target entry (abstract, [0013], [0044], [0080], [0083], [0098], [0100], Mangenelli et al. discloses storing user data in a first region with MLC memory storage and parity data in a second region with SLC memory storage. The Schema controller determines where to write both user and parity data. Parity data’s location is known and used to determine which parity data is related to which user data.).
Consider claim 6, Mangenelli et al. discloses the memory system according to claim 5, wherein the superblock comprises at least one stripe, the first physical address points to a target stripe in a plurality of stripes of the target superblock, and the target stripe is configured to store the user data; wherein the memory controller is configured to: determine a corresponding second identifier in the index information based on a first identifier in the index information, wherein the first identifier is configured to indicate a position of the target stripe, and the second identifier is configured to indicate a position of the target entry; and obtain the target entry based on the second identifier (abstract, [0013], [0036], [0042], [0044], [0070], [0071], [0080], [0083], [0098], [0100], Mangenelli et al. discloses an MLC first memory region where data is striped diagonally across page lines and planes (superblock). The Schema controller determines where to write both user and parity data. Parity data’s location is known and used to determine which parity data is related to which user data.).
Consider claim 7, Mangenelli et al. discloses the memory system according to claim 5, wherein the memory controller is further configured to: obtain second metadata related to the check data from the memory device, wherein the second metadata comprises address information related to the user data; determine that an error occurs in the second physical address recorded in the target entry based on the address information in the second metadata does not match the first physical address; and reconstruct the target entry based on an error that occurs in the second physical address recorded in the target entry (abstract, [0013], [0036], [0040], [0042], [0044], [0070], [0071], [0080], [0083], [0088], [0098], [0100], Mangenelli et al. discloses not only parity data but also ECC data and when an uncorrectable error occurs parity data is used to recover the information subjected to the memory error.).
Consider claim 8, Mangenelli et al. discloses the memory system according to claim 1, wherein a memory cell in the first memory region is configured to store M-bit data; a memory cell in the second memory region is configured to store N-bit data; both M and N are integers greater than 1; and N is less than M (abstract, [0013], [0044], [0080], [0083], [0098], [0100], Mangenelli et al. discloses storing user data in a first region with MLC memory storage and parity data in a second region with SLC memory storage.).
Consider claim 9, Mangenelli et al. discloses the memory system according to claim 1, wherein the memory controller is further configured to: obtain the user data stored in the first memory region from the memory device; send a reading instruction comprising the second physical address to the memory device based on an error-correcting code check performed on the obtained user data fails; wherein the reading instruction indicates to read the check data stored in the second memory region; and perform a redundant array check on the user data by using the check data read from the second memory region (abstract, [0013], [0036], [0040], [0042], [0044], [0070], [0071], [0080], [0083], [0088], [0098], [0100], [0150], Mangenelli et al. discloses not only parity data but also ECC data and when an uncorrectable error occurs parity data is used to recover the information subjected to the memory error. ECC checks are performed and if a check fails the parity information is retrieved and the portions of the data item are recovered.).
Claims 18-20 are the method claims to system claims 1, 2 and 9 above and are rejected in the same manner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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