Prosecution Insights
Last updated: July 17, 2026
Application No. 19/066,485

DISPLAY DEVICE

Non-Final OA §DP
Filed
Feb 28, 2025
Priority
Feb 02, 2016 — JP 2016-018365 +5 more
Examiner
DHARIA, PRABODH M
Art Unit
Tech Center
Assignee
Magnolia White Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1081 granted / 1263 resolved
+25.6% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
15 currently pending
Career history
1276
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
68.8%
+28.8% vs TC avg
§102
12.1%
-27.9% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1263 resolved cases

Office Action

§DP
Detailed Office Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status: Please all the replies and correspondence should be addressed to Examiner’s new art unit 2629. Receipt is acknowledged of papers submitted on 02-28-2025 under new application being continuation of parent Application No. 18,337,538 filed June 06, 2023 matured to U.S. Patent No. 12,242,148; which is continuation of Application No. 17,106,802 filed November 30, 2020 matured to U.S. Patent No.11, 385, 489; which is continuation of Application No. 16/205.955 filed November 30. 2018 matured to U.S. Patent No.10, 871, 853; which in turn, is a continuation application of Application No. 15/400.498 filed on January 06, 2017 matured to U.S. Patent No. 10.175.8161, which have been placed of record in the file. Claims 1-19 is pending in this action. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. . 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c). Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-19 are rejected on the ground of nonstatutory double patenting over claims 1-19 of US patent No. 12,242,148 B2, if allowed, would improperly extend the “right to exclude” already granted in the patent. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Comparison of claims 1-19 of Instant application to claims 1-19 of US patent No. 12,242,148 B2 patented parent applications. Furthermore, there is no apparent reason why applicant was prevented from presenting claims corresponding to those of the instant application during prosecution of the application which matured into a patent. See In re Schneller, 397 F.2d 350, 158 USPQ 210 (CCPA 1968). See also MPEP § 804. Instant Application Number 19,066,485 US Patent Number 12,242,148 1. A display device comprising: a substrate; pixel electrodes on the substrate; common electrodes opposed to the pixel electrodes, one of the common electrodes overlapping some of the pixel electrodes and not overlapping others of the pixel electrodes; a first conductive wire that is connected to the one of the common electrodes via a contact hole; and a gate line supplying a scanning signal to the pixel electrodes, wherein the first conductive wire has a first overlapping portion overlapping a line located between the first conductive wire and the substrate, and the gate line overlaps the contact hole. . 1. A display device comprising: a substrate; pixel electrodes on the substrate; common electrodes opposed to the pixel electrodes, one of the common electrodes overlapping some of the pixel electrodes and not overlapping others of the pixel electrodes; a first conductive wire that is connected to the one of the common electrodes via a contact hole; and a gate line overlapping the first conductive wire, and supplying a scanning signal, wherein the first conductive wire has a first overlapping portion overlapping a line located between the first conductive wire and the substrate, and the gate line overlaps the contact hole and is located between the line and the substrate. Note the comparison of independent claim 1 of instant application, to patented parent application claim 1 of US patent No. 12,242,148 B2 to avoid 101 statutory double patenting rejections the claims limitation by curtailing the details and language has been changed. However, instant application independent claim limitations are described in independent claims of the parent applications. They both are claiming “A display device includes: a plurality of first electrodes arranged in a display region for displaying an image; a second electrode opposed to the first electrodes; a plurality of switching elements that are arranged in the display region and coupled to the first electrodes or the second electrode; a gate line for supplying a scanning signal for scanning the switching elements; a data line for supplying a signal to the switching elements that are coupled to the switching elements; and conductive wire that is opposed to the second electrode via an insulating layer and is coupled to the switching elements.”. Further other Claims 2-19 of instant application claims same or similar limitation as well as maps to one to one of claims 2-19 of US patent No. 12,242,148 B2. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is requested to review the cited prior art on USPTO 892. The prior art of Kim Hyunho et al. (US 20170192571) disclosure; paras. 38-168, discloses, a method of fabricating a display device with a built-in touch screen. The method includes, forming a gate electrode and a pixel electrode on a substrate according to a first mask process, forming an activation layer, a source electrode, and a drain electrode, and a touch sensing line on the substrate on which the gate electrode and the pixel electrode are formed, according to a second mask process, forming a protective layer on the substrate on which the touch sensing line is formed, and forming a first contact hole that exposes a portion of the pixel electrode and a second contact hole that exposes a portion of the touch sensing line according to a third mask process, and forming a common electrode that overlaps with the pixel electrode on the substrate in which the first and second contact holes are formed, according to fourth mask process. Thereby, it is possible to reduce the number of mask processes. The display device includes a gate line extending along a first direction on a substrate, a data line extending along a second direction directly on an insulation layer on the substrate, and a subpixel at an intersection of the gate line and the data line. The subpixel includes a pixel electrode, and a transistor including a gate electrode on the substrate, a part of the insulation layer on the gate electrode, a semiconductor layer on the part of the gate insulation layer, a drain electrode on the semiconductor layer, and a source electrode on the semiconductor layer. The drain electrode is electrically connected to the pixel electrode, and the source electrode is electrically connected to the data line. The display device also includes a common electrode overlapping with the pixel electrode, and a touch sensing line directly on the insulation layer. The touch sensing line is electrically connected to the common electrode. The prior art of AHN JungEun et al. (US 20170160852 A1) disclosure; paras. 41-154, discloses, a display device having a touchscreen panel integrated therewith and a method of fabricating the same, the display panel being configured to simplify a fabrication process thereof and improve an aperture ratio.  A display device may include: a first substrate, a plurality of gate lines, a plurality of data lines, a thin film transistor, a first electrode, a second electrode and a touch signal line. The plurality of gate lines and the plurality of data lines are on the first substrate to define a plurality of pixels. The thin film transistor includes a source electrode, a drain electrode and a gate electrode at the sub-pixels. The first electrode is disposed on the sub-pixels. The second electrode is overlapped with the first electrode. The touch signal line is parallel to the data line, wherein a width of the touch signal line is wider than a width of the data line. The second electrode functions as a common electrode in a display mode and functions as a touch electrode in a touch mode. The second electrode is block-shaped pattern or a pattern including toothed portions. The first electrode is connected to one of the drain electrode or the source electrode.  The first electrode is block-shaped pattern or a pattern including toothed portions. The display device includes a protective layer between the first electrode and the second electrode.  The display device includes a protective layer between the touch signal line and the data line. The second electrode is connected to the touch signal line through a contact hole. The contact hole is overlapped with a part of the gate line. The data line, the touch signal line, opposite edges of the first electrode and opposite edges of the second electrode are parallel to one another.  The display device includes a second substrate opposing the first substrate, and the second substrate includes a plurality of color filters facing the first electrode.  An orthogonal projection of the touch signal line on the second substrate is positioned between a plurality of orthogonal projections of the color filters on the second substrate.  An orthogonal projection of the data line on the second substrate is positioned between a plurality of orthogonal projections of the color filters on the second substrate. A distance between each two of the plurality of the color filters is larger than the width of the touch signal line or the data line.  The touch signal line, the data line and the second electrode overlapped with a part of the gate line. The fabrication process of the display device having a touchscreen panel integrated therewith and improve the aperture ratio of the display device. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRABODH M DHARIA whose telephone number is (571)272-7668. The examiner can normally be reached Monday -Friday 9:00 AM to 5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Any response to this action should be mailed to: Commissioner of Patents and Trademarks P.O. Box 1450 Alexandria VA 22313-1450 /Prabodh M Dharia/ Primary Examiner Art Unit 2629 06-23-2026
Read full office action

Prosecution Timeline

Feb 28, 2025
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
91%
With Interview (+5.4%)
2y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1263 resolved cases by this examiner. Grant probability derived from career allowance rate.

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