DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13, and 24 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Gao et al (US 2019/0081772).
Regarding claim 1, Gao et al teach an apparatus (see figure 3), comprising: a data sampling circuit (see figure 3 ADC 304) comprising: a sampling clock deviation (see figure 3); and a sampling clock (see figure 3, output of component 326); a clock control circuit (see figure 3) configured to: determine the sampling clock deviation (see figure 3, component 310 “phase detector”); and generate a first clock control signal based on the sampling clock deviation (see figure 3, output of component 318); and a clock recovery circuit (see figure 3) configured to: adjust the sampling clock based on the first clock control signal to obtain an adjusted sampling clock (see figure 3, component 320); obtain, based on the adjusted sampling clock, a clock signal (see figure 3, component 305); and send the clock signal to the data sampling circuit (see figure 3), wherein the data sampling circuit is configured to sample an input analog signal based on the clock signal (see figure 3, ADC 304).
Regarding claim 13, Gao et al teach a method, applied to a communication apparatus (see figure 3 and 4), and comprising: determining, by a clock control circuit of the communication apparatus (see figure 3 and 4), a sampling clock deviation of a data sampling circuit of the communication apparatus (see figure 3, component 310 “phase detector”); generating, by the clock control circuit, a first clock control signal based on the sampling clock deviation (see figure 3, output of component 318); adjusting, by a clock recovery circuit of the communication apparatus (see figure 3), a sampling clock of the data sampling circuit based on the first clock control signal to obtain an adjusted sampling clock (see figure 3, component 320); obtaining, based on the adjusted sampling clock, a clock signal (see figure 3, component 305); sending, by the clock recovery circuit, the clock signal to the data sampling circuit (see figure 3); and sampling, by the data sampling circuit, an input analog signal based on the clock signal (see figure 3, ADC 304).
Regarding claim 24, Gao et al teach a computer program product comprising instructions that are stored on a non-transitory computer-readable medium and that, when executed by one or more processors, cause a communication apparatus (see figure 3 and 4) to: determine, by a clock control circuit of the communication apparatus, a sampling clock deviation of a data sampling circuit of the communication apparatus (see figure 3, component 310 “phase detector”); generate, by the clock control circuit, a first clock control signal based on the sampling clock deviation (see figure 3, output of component 318), wherein the first clock control signal adjusts a sampling clock of the data sampling circuit (see figure 3 and 4); adjust, by a clock recovery circuit of the communication apparatus, the sampling clock of the data sampling circuit based on the first clock control signal (see figure 3, component 320); send, by the clock recovery circuit, a clock signal to the data sampling circuit (see figure 3 component 305); and sample, by the data sampling circuit, an input analog signal based on the clock signal (see figure 3, ADC 304).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al (US 2019/0081772) in view of Singh (US 2020/0251823).
Regarding claim 2, which inherits the limitations of claim 1, Gao et al further teach wherein the first clock control signal indicates that, the clock signal is a target clock signal, and the target clock signal is capable of generating a sampling clock expected by the data sampling circuit (see figure 3 and 4 and paragraph 0024 – 0027). Gao does not expressly disclose using a threshold to determine the control signal. However, in analogous art, Singh teaches a clock data recovery system that uses a threshold (see figure 5, and paragraph 0079) and wherein when the first clock control signal indicates that the sampling clock deviation is less than a first threshold, the clock signal is a target clock signal, and the target clock signal is capable of generating a sampling clock expected by the data sampling circuit (see paragraph 0079). Therefore, it would have been obvious to an ordinary skilled in the art at the time the invention was filed to use a threshold to determine the use of correction operation. The motivation of suggestion to do so is to reduce the computational complexity of the CDR.
Regarding claim 14, which inherits the limitations of claim 13, the claimed method including the features corresponds to subject matter mentioned above in the rejection of claim 2 is applicable hereto.
Allowable Subject Matter
Claims 3 – 12, and 15 – 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAISON JOSEPH whose telephone number is (571)272-6041. The examiner can normally be reached M-F 8 - 4.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached at 571 272 3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JAISON . JOSEPH
Primary Examiner
Art Unit 2633
/JAISON JOSEPH/ Primary Examiner, Art Unit 2633
Prosecution Insights