DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 7746703 B2) in view of Han (US 2018/0173432 A1) in view of Sity (US 2022/0164297-A1).
In regards to claim 1, Kim teaches:
A memory comprising: a cell array including a plurality of memory cells and providing read data from the plurality of memory cells selected by row and column addresses; (Abstract, A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns.) as "fail" when the number of the plurality of multi-bit data groups determined as "fail" by the pass/fail determination circuit is greater than or equal to a first threshold value. (37, The program controller 171 controls the address generating circuit 160 as described above until the number of fail data bits input from the fail data bit detector 172 is greater than the reference value Ref.)
Kim fails to teach:
and a section fail determination circuit configured to determine section fail information of sections, which correspond to the row and column addresses and each section associated with one of the plurality of multi-bit data groups,
However, Han teaches:
and a section fail determination circuit configured to determine section fail information of sections, which correspond to the row and column addresses and each section associated with one of the plurality of multi-bit data groups, (0831, an activation circuit may be configured to activate one group of memory mats without activating another group of memory mats that share the same memory lines—or at least are coupled to different memory line segments that have a same line address.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Han, which teaches a read operation method in order improve reliability and efficiency. (Han: 0003, it takes a long time and the performance of a memory system including the nonvolatile memory is reduced.)
Kim in view of Han fails to teach:
a pass/fail determination circuit configured to divide the read data into a plurality of multi-bit data groups and to determine whether each multi-bit data group is "pass" or "fail";
However, Sity teaches:
a pass/fail determination circuit configured to divide the read data into a plurality of multi-bit data groups and to determine whether each multi-bit data group is "pass" or "fail"; (0079, The memory device MD may perform a logical operation on pieces of data read at two adjacent voltage levels from among the plurality of different voltage levels and may count the number of memory cells existing in each of a plurality of sections based on a result of the logical operation.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Sity, which teaches an integrated circuit for memory security in order improve hardware used to analyze data. (Sity: 0007, if the new chips are designed to operate with current data handling methods, they will have poor performance because current methods can limit the chip's ability to handle parallel operations.)
With regards to claim 2, Kim in view of Han in view of Sity teaches the memory of claim 1 and teaches:
wherein a read operation is performed multiple times changing one or more values of the row and column addresses, and a fail determination operation of the pass/fail determination circuit and the section fail determination circuit is performed whenever the read operation is performed. (15: Until all the memory cells are programmed within the predetermined number of times, the program loops are repeatedly performed. The program verify operation is essentially the same in the read operation except that read data are not output.)
With regards to claim 3, Kim teaches the memory of claim 2.
Kim fails to teach:
further comprising: a filtering circuit configured to filter the section fail information generated for each of the row and column addresses; and an output circuit configured to output a filtering result of the filtering circuit.
However, Han teaches:
further comprising: a filtering circuit configured to filter the section fail information generated for each of the row and column addresses; and an output circuit configured to output a filtering result of the filtering circuit. (1322, The filtering units may perform filtering operations such as comparing a value of a field to a threshold, comparing a value of a field to a predefined value, determining if a value of a field is within a predefined range, and the like.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Han, which teaches a read operation method in order improve reliability and efficiency. (Han: 0003, it takes a long time and the performance of a memory system including the nonvolatile memory is reduced.)
With regards to claim 4, Kim in view of Han in view of Sity teaches the memory of claim 3.
Kim fails to teach:
wherein when a filtering mode is set, the filtering circuit maintains section fail information corresponding to predetermined target row and column addresses as they are and processes remaining section fail information as "pass".
However, Han teaches:
wherein when a filtering mode is set, the filtering circuit maintains section fail information corresponding to predetermined target row and column addresses as they are and processes remaining section fail information as "pass". (1322, The filtering units may perform filtering operations such as comparing a value of a field to a threshold, comparing a value of a field to a predefined value, determining if a value of a field is within a predefined range, and the like.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Han, which teaches a read operation method in order improve reliability and efficiency. (Han: 0003, it takes a long time and the performance of a memory system including the nonvolatile memory is reduced.)
With regards to claim 5, Kim in view of Han in view of Sity teaches the memory of claim 4.
Kim fails to teach:
wherein the predetermined target row and column addresses have values of row and column addresses located in a diagonal portion of the cell array.
However, Han teaches:
wherein the predetermined target row and column addresses have values of row and column addresses located in a diagonal portion of the cell array. (0314 & 1322In a partial tile connection, the data from the diagonal adjacents may be passed through other adjacent processor subunits connected to the processor subunit. The filtering units may perform filtering operations such as comparing a value of a field to a threshold, comparing a value of a field to a predefined value, determining if a value of a field is within a predefined range, and the like.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Han, which teaches a read operation method in order improve reliability and efficiency. (Han: 0003, it takes a long time and the performance of a memory system including the nonvolatile memory is reduced.)
With regards to claim 6, Kim in view of Han in view of Sity teaches the memory of claim 3 and teaches:
wherein when a filtering mode is set and the number of sections in which the section fail information is "fail" in an N number of adjacent rows is greater than or equal to a threshold value (where "N" is an integer greater than or equal to 2), the filtering circuit maintains section fail information of sections in the N number of adjacent rows as they are and assigns a "pass" value to sections of remaining rows. (40: The flash memory device may include a memory cell array having multiple memory cells arranged in rows and columns; a pass/fail check circuit for verifying whether data bits selected by a column address during a column scan operation have program data values.)
With regards to claim 7, Kim in view of Han in view of Sity teaches the memory of claim 3 and teaches:
herein when a filtering mode is set and the number of sections in which section fail information is "fail" in an M number of adjacent columns is greater than or equal to a third threshold value (where "M" is an integer greater than or equal to 2),the filtering circuit maintains section fail information of sections in the M number of columns as they are and processes section fail information in sections in the remaining columns as "pass". (40: The flash memory device may include a memory cell array having multiple memory cells arranged in rows and columns; a pass/fail check circuit for verifying whether data bits selected by a column address during a column scan operation have program data values.)
With regards to claim 8, Kim in view of Han in view of Sity teaches the memory of claim 1.
Kim in view of Han fails to teach:
wherein the pass/fail determination circuit performs an XOR operation for each group and determines "pass" or "fail".
However, Sity teaches:
wherein the pass/fail determination circuit performs an XOR operation for each group and determines "pass" or "fail". (0082, the defence code operator 314 may perform an XOR operation on the first data RD1 and the second data RD2 based on a selection defence code.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Sity, which teaches an integrated circuit for memory security in order improve hardware used to analyze data. (Sity: 0007, if the new chips are designed to operate with current data handling methods, they will have poor performance because current methods can limit the chip's ability to handle parallel operations.)
In regards to claim 9, Kim teaches:
An operating method of a memory, the operating method comprising: reading data of memory cells selected by a row address and a column address; (Abstract, A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns.) determining whether data is "pass" or "fail" for each group; and generating section fail information of a section, which corresponds to the row and column addresses, (Abstract, The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit.) as "fail" when a number of groups from the plurality of groups determined as "fail" by a pass/fail determination circuit is greater than or equal to a first threshold value. (37, The program controller 171 controls the address generating circuit 160 as described above until the number of fail data bits input from the fail data bit detector 172 is greater than the reference value Ref.)
Kim fails to teach:
dividing the data read from the memory cells into a plurality of groups;
However, Han teaches:
dividing the data read from the memory cells into a plurality of groups; (0547, and dividing the number of words required simultaneously between multiple memory banks;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a memory cell array, a pass/fail check circuit and a control logic circuit of Kim with the teaching of Han, which teaches a read operation method in order improve reliability and efficiency. (Han: 0003, it takes a long time and the performance of a memory system including the nonvolatile memory is reduced.)
With regards to claim 10, Kim in view of Han teaches the operating method of claim 9 and corresponds to claim 2 as analyzed accordingly.
With regards to claim 11, Kim in view of Han teaches the operating method of claim 10 and corresponds to claim 3 as analyzed accordingly.
With regards to claim 12, Kim in view of Han teaches the operating method of claim 11 and corresponds to claim 4 as analyzed accordingly.
With regards to claim 13, Kim in view of Han teaches the operating method of claim 12 and corresponds to claim 5 as analyzed accordingly.
With regards to claim 14, Kim in view of Han teaches the operating method of claim 11 and corresponds to claim 6 as analyzed accordingly.
With regards to claim 15, Kim in view of Han teaches the operating method of claim 11 and corresponds to claim 7 as analyzed accordingly.
With regards to claim 16, Kim in view of Han teaches the operating method of claim 9 and corresponds to claim 8 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Abiko (US-8599613-B2): a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.
Conclusion
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111
7/10/2026
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