Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show legible labels in figures 3B, 3E and 3G as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12302464 B1 in view of Crawley et al. (US 10193448 B1). The differences between claim 1 and similarly claim 10 of the current application and claim 1 and similarly claim 11 of U.S. Patent No. US 12302464 B1 is what the combiner is doing with the currents coming out of individual integrators from current sense amplifiers. The combiner associated with claim 1 of current application selects a highest current from one of the plurality of integrated sensed currents whereas the combiner associated with claim 1 of U.S. Patent No. US 12302464 B1 sums the plurality of currents from the individual integrated sensed currents. It would be a simple practice for a person of ordinary skill in the art before the effective filing date to place an individual integrator as described by fig. 6 of Crawley in between the individual inputs of the maximum select circuit 168 and the individual outputs of each operational amplifiers 144-148 as described by fig. 6 of Szczeszynski by allowing the calculation of a total current over a time period [col 9 lines 25-55] as opposed to an instantaneous current thereby improving an LED controlling circuits operational efficiency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Szczeszynski et al. (US 8169161 and Szczeszynski hereinafter.) in view of Crawley et al. (US 10193448 B1 and Crawley hereinafter.).
Regarding claim 1, A system for controlling a plurality of light-emitting diodes (LEDs) [fig. 6, LEDS 14-18] in an electronic device, the system comprising: LED control circuitry coupled to LED driver circuitry, the LED control circuitry comprising: a plurality of current sense amplifiers [fig. 6, operational amplifier 144-148, mosfets 132-136 and resistors 138-142], each current sense amplifier being configured to sense and amplify current received for an LED of the plurality of LEDS [col 13 lines 60-65]. Szczeszynski discloses further a combiner [maximum select circuit 168] configured to select a highest current [col 13 lines 14-19] and a comparator [comparator 170] configured to compare the highest current, selected by the combiner [col 13 lines 20-30], to a threshold [threshold 172]. Szczeszynski does not explicitly disclose the comparator as a latching comparator.
However, it would be a simple practice to for a person of ordinary skill in the art before the effective filing date to introduce positive feedback on the comparator as described by Szczeszynski to introduce hysteresis in the comparators behavior thereby causing the comparator to latch its output.
Szczeszynski does not explicitly disclose a plurality of integrators, each integrator of the plurality of integrators being coupled to an output of a respective current sense amplifier of the plurality of current sense amplifiers, each integrator being configured to integrate the current sensed and amplified by the respective current sense amplifier of the plurality of current sense amplifiers.
However, Crawley discloses [fig. 6] an integrator 154 accepting an LED current sense signal 151 and into a summer 161. It would be a simple practice for a person of ordinary skill in the art before the effective filing date to place an individual integrator as described by Crawley between the individual inputs of the maximum select circuit 168 and the individual outputs of each operational amplifiers 144-148 as described by Szczeszynski by allowing the calculation of a total current over a time period [col 9 lines 25-55] as opposed to an instantaneous current thereby improving an LED controlling circuits operational efficiency.
Regarding claim 2, Szczeszynski in view of Crawley discloses further comprising: the LED driver circuitry, the LED driver circuitry configured to generate current for the plurality of LEDs and provide the current to the plurality of current sense amplifiers [Szczeszynski, via DC-DC converter providing Vout on 12a].
Regarding claim 5, Szczeszynski in view of Crawley discloses all the features of claim 1 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the threshold is a maximum steady state current associated with producing an irradiance of 100 W/m2.
However, the error amplifier 170 of Szczeszynski, acting as a comparator, has a threshold of 2.5 voltage before going high, triggering an error state. This error state is associated with a max current through the LEDs so it would be obvious for a person of ordinary skill in the art to associates this error state with a desired maximum irradiance of the LEDs, for example 100 W/ m2. Therefore, it would have been obvious to one of ordinary skill in the art to associate this maximum current error state with a specific desired maximum irradiance of the LEDs, such as 100 W/m², as determining the optimum value of a known result-effective variable is a matter of routine optimization. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 6, Szczeszynski in view of Crawley discloses further wherein the comparator is configured to latch the at least the portion of the current to the one or more LEDs, when the highest current exceeds the threshold [Szczeszynski, col 13 lines 14-19], until a reset is issued [inputs on comparator being low, thereby resetting the comparator to output a low signal.].
Regarding claim 7, Szczeszynski in view of Crawley discloses the claimed invention except for wherein each integrator is configured to integrate the current sensed and amplified by the respective current sense amplifier of the plurality of current sense amplifiers minus a fixed direct current (DC) offset.
However, it is well known in the art that current integrators, integrating a current over time, will accumulate any small DC offset inherent with non-ideal analog circuitry. To prevent the integrator from saturating, it would be obvious for a person of ordinary skill in the art before the effective filing date to subtract a DC offset from a current integrator for non-ideal current integrators. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 8, Szczeszynski in view of Crawley discloses further wherein each current sense amplifier receives a reference voltage [Szczeszynski, fig. 6, reference voltage signal 156], and wherein each current sense amplifier is configured to bias the output around the reference voltage [inherent property of operational amplifier].
Regarding claim 9, Szczeszynski in view of Crawley discloses all the features in claim 8 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the reference voltage is generated by a buffered resistor divider.
However, the practice of using a voltage divider using series connected resistors with a voltage source thereby providing a reference voltage is well known in the art and it would be obvious to anyone trained in the art to use series connected resistors with a voltage source to provide the reference voltage being generated by a buffered resistor divider. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 10, Szczeszynski discloses a method for controlling a plurality of light-emitting diodes (LEDs) [fig. 6, LEDS 14-18] in an electronic device, the method comprising: receiving, by LED control circuitry [fig. 6, op amps 144-148, mosfets 132-136 and resistors 138-142], current for the plurality of LEDs; sensing and amplifying [via operational amplification], by a plurality of current sense amplifiers [fig. 6, op amps 144-148, mosfets 132-136 and resistors 138-142], the current received by the LED control circuitry [col 13 lines 60-65]. Szczeszynski discloses further selecting, by a combiner [maximum select circuit 168], a highest current from one of the plurality of integrators [col 13 lines 14-19]; comparing, by comparing,
However, it would be a simple practice for a person of ordinary skill in the art before the effective filing date to introduce positive feedback on the comparator as described by Szczeszynski to introduce hysteresis in the comparators behavior thereby causing the comparator to latch its output. Szczeszynski does not explicitly disclose integrating, by a plurality of integrators, the current sensed and amplified by the plurality of current sense amplifiers.
However, Crawley discloses [fig. 6] an integrator 154 accepting an LED current sense signal 151 and into a summer 161. It would be a simple practice for a person of ordinary skill in the art before the effective filing date to place an individual integrator as described by Crawley between the individual inputs of the maximum select circuit 168 and the individual outputs of each operational amplifiers 144-148 as described by Szczeszynski by allowing the calculation of a total current over a time period [col 9 lines 25-55] as opposed to an instantaneous current thereby improving an LED controlling circuits operational efficiency.
Regarding claim 11, Szczeszynski in view of Crawley discloses all the features regarding claim 10 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein each integrator is configured to integrate the current sensed and amplified by a respective current sense amplifier of the plurality of current sense amplifiers minus a fixed direct current (DC) offset.
However, it is well known in the art that current integrators, integrating a current over time, will accumulate any small DC offset inherent with non-ideal analog circuitry. To prevent the integrator from saturating, it would be obvious for a person of ordinary skill in the art before the effective filing date to subtract a DC offset from a current integrator for non-ideal current integrators. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 12, Szczeszynski in view of Crawley discloses further comprising: generating, by LED driver circuitry, the current for the plurality of LEDs; and providing the current to the plurality of current sense amplifiers [Szczeszynski, via DC-DC converter providing Vout on 12a].
Regarding claim 15, Szczeszynski in view of Crawley discloses all the features of claim 1 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the threshold is a maximum steady state current associated with producing an irradiance of 100 W/m2.
However, the error amplifier 170 of Szczeszynski, acting as a comparator, has a threshold of 2.5 voltage before going high, triggering an error state. This error state is associated with a max current through the LEDs so it would be obvious for someone trained in the art to associates this error state with a desired maximum irradiance of the LEDs, for example 100 W/ m2. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 16, Szczeszynski in view of Crawley discloses further wherein the latching comparator circuitry is configured to latch the at least the portion of the current to one or more of the plurality of LEDs, when the highest current exceeds the threshold [Szczeszynski, col 13 lines 14-19], until a reset is issued [inputs on comparator being low, thereby resetting the comparator to output a low signal.].
Regarding claim 17, Szczeszynski in view of Crawley discloses further wherein each current sense amplifier receives a reference voltage [Szczeszynski, fig. 6, reference voltage signal 156], and wherein each current sense amplifier is configured to bias an output around the reference voltage [inherent property of operational amplifier].
Regarding claim 18, Szczeszynski in view of Crawley discloses all the features in claim 8 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the reference voltage is generated by a buffered resistor divider.
However, the practice of using a voltage divider using series connected resistors with a voltage source thereby providing a reference voltage is well known in the art and it would be obvious to anyone trained in the art to use series connected resistors with a voltage source to provide the reference voltage being generated by a buffered resistor divider wherein the reference voltage is generated by a buffered resistor divider. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 19, Szczeszynski in view of Crawley discloses further wherein the latching comparator circuitry includes A) a comparator [Szczeszynski, fig. 6, comparator 170] and B) multiple resistors [inherent with latching comparators utilizing hysteresis via positive feedback using resistors], the multiple resistors being included in a positive feedback loop [inherent with latching comparators utilizing hysteresis via positive feedback using resistors].
Regarding claim 20, Szczeszynski in view of Crawley discloses all the features regarding claim 19 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein at least two of the multiple resistors are connected in series when the latching comparator has a low output, and wherein the at least two of the multiple resistors are connected in parallel when the latching comparator has a high output.
However, the use of series and parallel connected resistor networks is well known in the art along with determining equivalent resistances from these interconnections are being well known in the art, it would be a simple practice for someone trained in the art before the effective filing date to have a positive feedback resistor network utilizing differing combinations of series and parallel connected resistors in the positive feedback loop of the latching comparator to have this claimed feature set. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Szczeszynski in view of Crawley further in view of Liu et al. (US 11922892 B2 and Liu hereinafter.).
Regarding claim 3, Szczeszynski in view of Crawley discloses all the features of claim 1 as indicated above. Szczeszynski in view of Crawley discloses does not explicitly disclose wherein the electronic device is an artificial reality head-mounted display having a rigid body configured to be worn on a face of a user.
However, Liu discloses [fig. 20] wherein the electronic device is an artificial reality head-mounted display having a rigid body configured to be worn on a face of a user [system 2000]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Szczeszynski in view of Crawley to include the electronic device as taught by Liu to improve a user experience of an electronic device.
Regarding claim 4, Szczeszynski in view of Crawley further in view of Liu discloses further wherein the plurality of LEDs are configured and positioned to illuminate at least one of an eye of the user, the face of the user, or both [as shown in fig. 20 of Liu].
Regarding claim 13, Szczeszynski in view of Crawley discloses all the features regarding claim 10 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the electronic device is an artificial reality head-mounted display having a rigid body configured to be worn on a face of a user.
However, Liu discloses [fig. 20] wherein the electronic device is an artificial reality head-mounted display having a rigid body configured to be worn on a face of a user [system 2000]. Therefore, it would have been obvious to for a person of ordinary skill in the art before the effective filing date to modify the invention as described by Szczeszynski in view of Crawley to include the electronic device as taught by Liu to improve a user experience of an electronic device.
Regarding claim 14, Szczeszynski in view of Crawley discloses all the features of claim 1 as indicated above. Szczeszynski in view of Crawley does not explicitly disclose wherein the threshold is a maximum steady state current associated with producing an irradiance of 100 W/m2.
However, the error amplifier 170 of Szczeszynski, acting as a comparator, has a threshold of 2.5 voltage before going high, triggering an error state. This error state is associated with a max current through the LEDs so it would be obvious for someone trained in the art to associates this error state with a desired maximum irradiance of the LEDs, for example 100 W/ m2. Therefore, it would have been obvious to one of ordinary skill in the art to associate this maximum current error state with a specific desired maximum irradiance of the LEDs, such as 100 W/m², as determining the optimum value of a known result-effective variable is a matter of routine optimization. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Lin (US 10804865 B1) is cited to teach current integration and amplification.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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