DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: Paragraph 0078 of the specification refers to element 110 as Q node controller and element 120 as QB node controller (see fig. 4; element 110); Further paragraph 0082 describes Q node controller 110 comprising transistors shown by element 130 in fig. 4. Similarly, paragraph 0098 describes QB node controller 110 comprising transistors shown by element 140 in fig. 4. Appropriate correction is required.
Claim Objections
Claim 9 is objected to because of the following informalities: claim 9 includes limitation “wherein a gate electrode of the first control transistor is connected to a first control signal line to which a first control signal is supplied, a source electrode of the first control transistor is connected to the output terminal of the n-th stage, and a drain electrode of the first control transistor is connected to the input terminal of the n+1-th stage”. n-1th stage is mistakenly written as n+1-the stage. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 12 recites the limitation " wherein the first active area and the second active area have different driving frequencies". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ZHANG et al (US Pub 2020/0082765).
With respect to claim 1, ZHANG discloses a display apparatus, (fig. 15; discloses display device; par 0076; discloses an embodiment of the disclosure further provides a display device including the display panel above according to the embodiment of the disclosure. The display device according to this embodiment can be an array substrate, or can be a terminal display device, e.g., a phone, a computer, a TV set, or another display device with a display function) comprising: a display panel including an active area in which a plurality of pixels is disposed and a non- active area adjacent to the active area (fig. 14; display area AA, non-display area BB; par 0073; discloses the display panel includes a display area AA and a non-display area BB, where the display area AA includes gate lines G, and data lines S intersecting with and insulated from the gate lines G, and the non-display area BB includes the scan circuit gr according to any one of the embodiments above of the disclosure); and a gate driver configured to output an output signal in a forward direction or a backward direction according to a scan mode, (par 0007; discloses disclosure provide a scan circuit, a display panel, and a display device to perform bidirectional scanning; par 0062; discloses A forward input terminal INF of the first-stage shift register element VSR1 in the forward scan direction is connected with a forward scan frame trigger terminal STVF, and forward input terminals INF of the other-stage shift register element VSRn than the first-stage shift register element VSR1 is connected respectively with the signal output terminal outn−1 corresponding to its preceding shift register element VSRn−1 in the forward scan direction; par 0063; discloses A backward input terminal INB of the last-stage shift register element VSRN in the forward scan direction is connected with a backward scan frame trigger terminal STVB, and backward input terminal INB of the other-stage shift register element VSRn than the last-stage shift register element VSRN is connected with the signal output terminal outn+1 corresponding to its preceding stage shift register element VSRn+1 in the backward scan direction) wherein the gate driver includes: a plurality of stages (fig. 11; discloses gate driver comprises plurality of stages VSR1-VSRN); and a scan direction controller connected between the plurality of stages to transmit the output signal output from an n-th stage to any one of an n-1-th stage or an n+1-th stage according to the scan mode, where n is an integer (par 0065; discloses in the scan circuit according to the embodiment of the disclosure, the gate driver circuit further includes a forward scan control circuit and a backward scan control circuit; par 0066; discloses The forward scan control circuit includes forward scan switch transistors T3 and a forward scan control line Conf, where each of the forward scan switch transistors T3 has a gate connected with the forward scan control line Conf, and the forward scan switch transistors T3 are configured to control the respective shift register elements VSR1 to VSRN to output the drive signal sequentially in the forward scan direction, under the control of the forward scan control line Conf; par 0067; discloses The backward scan control circuit includes backward scan switch transistors T4 and a backward scan control line Conb, the backward scan switch transistors T4 are configured to control the shift register elements VSR1 to VSRN to output the drive signal sequentially in the backward scan direction, under the control of the backward scan control line Conb).
With respect to claim 8, ZHANG discloses wherein the scan direction controller includes: a first control transistor connected between an output terminal of the n-th stage and an input terminal of the n-1-th stage, among the plurality of stages (fig. 13; transistor T4; par 0067; discloses the backward scan control circuit includes backward scan switch transistors T4 and a backward scan control line Conb, the backward scan switch transistors T4 are configured to control the shift register elements VSR1 to VSRN to output the drive signal sequentially in the backward scan direction, under the control of the backward scan control line Conb.); and a second control transistor connected between the output terminal of the n-th stage and an input terminal of the n+1-th stage, among the plurality of stages (fig. 13; transistor T3; par 0066; discloses the forward scan control circuit includes forward scan switch transistors T3 and a forward scan control line Conf, where each of the forward scan switch transistors T3 has a gate connected with the forward scan control line Conf, and the forward scan switch transistors T3 are configured to control the respective shift register elements VSR1 to VSRN to output the drive signal sequentially in the forward scan direction, under the control of the forward scan control line Conf. ).
With respect to claim 9, ZHANG discloses wherein a gate electrode of the first control transistor is connected to a first control signal line to which a first control signal is supplied, a source electrode of the first control transistor is connected to the output terminal of the n-th stage, and a drain electrode of the first control transistor is connected to the input terminal of the n+1-th stage (fig. 3; discloses a gate electrode of the transistor T4 is connected to the control line Comb and a first electrode is connected to the output terminal of nth stage and second electrode is connected to the input terminal of n-1th stage) and wherein a gate electrode of the second control transistor is connected to a second control signal line to which a second control signal is supplied, a source electrode of the second control transistor is connected to an output terminal of the n-th stage, and a drain electrode of the second control transistor is connected to an input terminal of the n+lth stage (fig. 3; discloses a gate electrode of the transistor T3 is connected to the control line Comf and a first electrode is connected to the output terminal of nth stage and second electrode is connected to the input terminal of n+1th stage).
With respect to claim 10, ZHANG discloses wherein when the first control signal is at a high level, the second control signal is at a low level and when the first control signal is at a low level, the second control signal is at a high level (see fig. 12 and 13; discloses first control signal Con1 and second control signal Con2 are opposite of each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al (US Pub 2020/0082765) and Hu et al (US Pub 2016/0372070).
With respect to claim 2, ZHANG doesn’t expressly disclose wherein the plurality of stages includes: a pull-down unit connected to a Q node; a pull-up unit connected to a QB node; a Q node controller configured to control a voltage of the Q node according to the scan mode; and a QB node controller configured to control a voltage of the QB node according to the scan mode;
In the same field of endeavor, Hu discloses gate driving circuit for a display device capable of bi-directional driving (see abstract); Hu discloses wherein the plurality of stages includes (fig. 4; discloses plurality of stages of the gate driving circuit): a pull-down unit connected to a Q node (fig. 2; discloses each stage includes a pull-up transistor T1 connected to PU node (i.e. Q node)); a pull-up unit connected to a QB node (fig. 2; discloses pull-down transistor T2 connected to PD node (i.e. QB node)); a Q node controller configured to control a voltage of the Q node according to the scan mode (fig. 2; discloses transistor T6; par 0043; discloses The sixth transistor T6 controls the voltage at the pull-up node PU to continuously pull down the PU node when the PD node is at the high level,); and a QB node controller configured to control a voltage of the QB node according to the scan mode (fig. 2; transistor T7; par 0043; discloses the seventh transistor T7 is a control transistor for the pull-down node PD, which maintains the PD node at the low level while the PU node is at the high level);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by ZHANG to form the gate driving circuit comprising plurality of stages having the circuit disclosed by Hu in order to sequentially generate plurality of gate signals for controlling the plurality of pixels in the display area of the display panel.
With respect to claim 3, ZHANG as modified by Hu discloses wherein the Q node controller controls a voltage of the Q node according to a clock signal, an output signal of an n-1-th stage, an output signal of an n+1-th stage, a first control signal, and a second control signal (Hu; fig. 2; discloses gate electrode of the transistor T6 is connected to an electrode of the transistor T5 that is controlled by clock ck3; and one electrode of transistor T6 is connected to common electrode of transistor T3 and T4 that receives an output signal of an n-1-th stage, an output signal of an n+1-th stage, a first control signal ck4, and a second control signa ck2).
With respect to claim 5, ZHANG as modified by Hu discloses wherein the QB node controller controls a voltage of the Q node according to a clock signal, an output signal of an n-1-th stage, an output signal of an n+1-th stage, a first control signal, and a second control signal (Hu; fig. 2; discloses one of the electrode of the transistor T6 is connected to an electrode of the transistor T5 that is controlled via clock ck3 and gate electrode of the transistor T6 is connected to common electrode of transistor T3 and T4 that receives an output signal of an n-1-th stage, an output signal of an n+1-th stage, a first control signal ck4, and a second control signa ck2 ).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al (US Pub 2020/0082765) and Kobayashi (US Pub 2011/0164003).
With respect to claim 11, ZHANG discloses wherein the first control signal and the second control signal are changed from a high level to a low level or from a low level to a high level in order to switch the scanning direction (ZHANG; see fig. 12 and 13; discloses control signal con1 and con2 are switched from a high level to a low level or from a low level to a high level in order to switch the scanning direction);
ZHANG doesn’t expressly disclose wherein the active area includes a first active area and a second active area and wherein the first control signal and the second control signal are changed from a high level to a low level or from a low level to a high level, in accordance with a boundary line between the first active area and the second active area;
In the same field of endeavor, Kobayashi discloses a display device and driving method (see abstract); Kobayashi discloses wherein the active area includes a first active area and a second active area (fig. 1A; discloses display area includes first area 16a and second area 16b) and wherein the first control signal and the second control signal are changed from a high level to a low level or from a low level to a high level, in accordance with a boundary line between the first active area and the second active area (fig. 9; par 0095; discloses the scanning wirings of the upper side region are scanned in an opposite direction to the scanning wirings of the lower side region, and therefore the selection timings of the scanning wirings near the boundary in the upper side region and the lower side region can be brought closer together (or made equal). Hence, when scanning is performed as shown in FIG. 9A, the blank period is provided only at the end time of the scanning, as shown in FIG. 13C, and when scanning is performed as shown in FIG. 9B, the blank period is provided only at the start time of the scanning, as shown in FIG. 13D. Accordingly, the total blank period can be shortened (halved) in comparison with the second example);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by ZHANG to divide the display into regions and drive each regions independently in any direction as disclosed by Kobayashi in order to allow content to be updated partially in the panel, hence conserving power while improving the image quality when an image apparatus is using dual scanning system.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al (US Pub 2020/0082765) and SEO et al (US Pub 2021/0035488).
With respect to claim 12, ZHANG doesn’t expressly disclose wherein the first active area and the second active area have different driving frequencies;
In the same field of endeavor, SEO discloses a display device and control method (see abstract); SEO discloses the display area comprising first active area and second active area wherein the first active area and the second active area have different driving frequencies (par 0052; discloses The multi-frequency driver 200 may determine (e.g., automatically determine) a first area including the video and a second area in which the static image is displayed, and may control the display device 1000 to apply different refresh rates to the first area and the second area. See par 0048-0049 as well);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by ZHANG to divide the display area into parts and drive each part at different refresh rates as disclosed by SEO in order to reduce the power consumption without increasing a cost for detecting the boundary pixel row detection.
Allowable Subject Matter
Claims 4, 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is objected for being dependent on claim 6.
With respect to claim 4, ZHANG alone or in view of other prior art of record fails to disclose wherein the Q node controller includes: a 1-1-th transistor connected between a forward input terminal and a Q1 node; a 1-2-th transistor connected between the Q1 node and the Q node; a 1-3-th transistor connected between a clock signal line and the 1-2-th transistor; a 1-4-th transistor connected between a backward input terminal and a Q2 node; a 1-5-th transistor connected between the Q2 node and the Q node; and a 1-6-th transistor connected between the clock signal line and the 1-5-th transistor and it would not have been obvious to one having ordinary skill in the art to modify the invention disclosed by ZHANG to arrive at the claimed invention as the final result would have been unpredictable. Therefore claim 4 comprises allowable subject matter.
With respect to claim 6, ZHANG alone or in view of other prior art of record fails to disclose wherein the QB node controller includes: a 2-1-th transistor connected between a QB 1 node and a gate high signal line; a 2-2-th transistor connected between the QB 1 node and the gate high signal line; a 2-3-th transistor connected between a clock signal line and the QB node; a 2-4-th transistor connected between the gate high signal line and the QB node; and a first capacitor connected between the clock signal line and the QB 1 node and it would not have been obvious to one having ordinary skill in the art to modify the invention disclosed by ZHANG to arrive at the claimed invention as the final result would have been unpredictable. Therefore claim 4 comprises allowable subject matter.
Conclusion
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/SUJIT SHAH/Examiner, Art Unit 2624