DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/19/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims are drawn to instructions that are stored in a memory, i.e. "computer readable medium". The broadest reasonable interpretation of a claim drawn to a computer readable medium covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media. Because the broadest reasonable interpretation covers a signal per se, a rejection under 35 USC 101 is appropriate as covering non-statutory subject matter. See MPEP 2106 and In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007).
The Examiner suggests that Applicant amends the claims as follows: "non-transitory computer readable medium containing computer instructions stored therein for causing a computer processor to perform".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 2018/0358970 A1).
Regarding claim 1, Wang teaches a method performed by a first global switch box (GSB) (Fig. 2A, [0010] a clock distribution and transmission circuitry, Fig. 4A, GSB, i.e. the clock distribution and transmission circuit represented by the box in the center of Logic Tile 1), the method comprising:
receiving, via a first plane, a clock signal (Fig. 4A, Clock 1 Signal Input) via a first clock index (index 1) of a set of clock indices (indices 1, 3, 5, 7) configured to receive clock signals via a clock routing channel ([0010] clock paths);
transitioning the clock signal (index 1) to a second plane associated with a second clock index (index 3); and
providing via the second plane, the clock signal to a second GSB (GSB in Logic Tile 2) via the second clock index (index 3).
Regarding claim 2, all the limitations of claim 1 are taught by Wang.
Wang further teaches the method, wherein transitioning the clock signal to the second plane comprises: transitioning the clock signal to the second plane via a bi-directional interplane connection (Fig. 2A, Wo and Wu, U-turn circuit).
Regarding claim 3, all the limitations of claim 2 are taught by Wang.
Wang further teaches the method, wherein the first clock index is connected to the second plane via multiple interplane connections with clock indices for the second plane (Fig. 2A, muxes within the center box).
Regarding claim 4, all the limitations of claim 1 are taught by Wang.
Wang further teaches the method, comprising: providing the clock signal to a third GSB via the first plane (Fig. 4A, Logic Tile 3).
Regarding claim 5, all the limitations of claim 1 are taught by Wang.
Wang further teaches the method, wherein the first clock index is associated with a first global input block (GIB) (Fig. 4A, Figs. 2A~C, input circuits on East clock path), and wherein the second clock index is associated with a second GIB (Fig. 4A, Figs. 2A~C, input circuits on West/North/South clock path).
Regarding claim 6, all the limitations of claim 1 are taught by Wang.
Wang further teaches the method, wherein the first GSB comprises a source GSB (Fig. 2A, a mux that drives an output to East or West or North or South).
Regarding claim 7, all the limitations of claim 6 are taught by Wang.
Wang further teaches the method, wherein the source GSB is co-located with a root GSB (Fig. 2A, the center mux that drives Tile clock).
Regarding claim 8, all the limitations of claim 1 are taught by Wang.
Wang further teaches the method, wherein providing the clock signal to the second GSB via the second clock index (Fig. 4A, index 3) comprises: providing the clock signal on a clock route (Fig. 2A, internal clock route connecting 5 muxes within the center box) that is configured as a distribution track for a root GSB (Fig. 2A, the center mux that drives Tile clock) to distribute the clock signal after receipt from the first GSB
Regarding claim 11, Wang teaches a system comprising:
a first global switch box (GSB) (Fig. 2A, [0010] a clock distribution and transmission circuitry, Fig. 4A, GSB, i.e. the clock distribution and transmission circuit represented by the box in the center of Logic Tile 1) of a programmable logic device (Fig. 1A), the first GSB to:
receive, via a first plane, a clock signal (Fig. 4A, Clock 1 Signal Input) via a first clock index (index 1) of a set of clock indices (indices 1, 3, 5, 7) configured to receive clock signals via a clock routing channel ([0010] clock paths);
transition, via a bi-directional interplane connection (Fig. 2A, Wo and Wu, U-turn circuit), the clock signal (index 1) to a second plane associated with a second clock index (index 3); and
provide, via the second plane, the clock signal to a second GSB (GSB in Logic Tile 2) via the second clock index (index 3).
Regarding claim 12, all the limitations of claim 11 are taught by Wang.
Wang further teaches the system, wherein the first GSB comprises: a set of clock indices configured to receive clock signals via a clock routing channel (Fig. 2A, East, West, South, North Clock paths and corresponding U-turn paths), and a set of interplane connections (Fig. 2A, muxes within the center box) that provide links between each clock index and multiple additional clock indices.
Regarding claim 13, all the limitations of claim 11 are taught by Wang.
Wang further teaches the system, wherein the first clock index (Fig. 4A, index 1) is connected to the second plane via multiple interplane connections (Fig. 2A, muxes within the center box) with clock indices for the second plane (Fig. 4A, indices 3, 5, 7 associated with the center box).
Regarding claim 14, all the limitations of claim 11 are taught by Wang.
Wang further teaches the system, wherein to provide the clock signal to the second GSB via the second clock index, the first GSB is to: provide the clock signal on a clock route that is configured as a distribution track for a root GSB to distribute the clock signal after receipt from the first GSB (Fig. 4A, horizontal track extending through Logic Tile 1~3).
Regarding claim 15, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 15 is rejected under the same rationale as claim 1 above.
Regarding claim 16, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 16 is rejected under the same rationale as claim 4 above.
Regarding claim 17, this claim has substantially the same subject matter as that in claim 5. Therefore, claim 17 is rejected under the same rationale as claim 5 above.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 6. Therefore, claim 18 is rejected under the same rationale as claim 6 above.
Regarding claim 19, this claim has substantially the same subject matter as that in claim 7. Therefore, claim 19 is rejected under the same rationale as claim 7 above.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 8. Therefore, claim 20 is rejected under the same rationale as claim 8 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2018/0358970 A1) in view of Natu (US 2019/0007047 A1).
Regarding claim 9, all the limitations of claim 1 are taught by Wang.
Wang further teaches the system, wherein the first GSB is associated with a first set of clock domains of a programmable logic device (Fig. 4A, clock 1, a single clock domain).
Wang does not explicitly teach the system, wherein an additional GSB is associated with a second set of clock domains of the programmable logic device, and wherein the first set of clock domains and the second set of clock domains are separated by a boundary.
Natu teaches a system, wherein an additional GSB is associated with a second set of clock domains of the programmable logic device (Fig. 4B, [0012] Virtual Array 1 and Virtual Array 2), and wherein the first set of clock domains and the second set of clock domains are separated by a boundary (Logic Tile boundary between Virtual Array 1 and Virtual Array 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the multi-clock domain approach of Natu to the teachings of Wang in order to allow the flexibility in selecting available clock sources for different tiles or different regions or different functions while keeping the skew with control that allow orderly implementation of the functions or operations of the logic tile and/or communication with other logic tiles and the FPGA’s external inputs and outputs (Natu, [0004], [0016]-[0021], [0024]-[0032]).
Regarding claim 10, all the limitations of claim 9 are taught by Wang in view of Natu.
Natu further teaches the system, wherein a root GSB associated with the first set of clock domains is positioned off of the boundary (Fig. 4B, Virtual Array 1 and Virtual Array 2 are separated and receive different clocks).
Regarding claim 21, this claim has substantially the same subject matter as that in claim 9. Therefore, claim 21 is rejected under the same rationale as claim 9 above
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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