DETAILED ACTION
This is in response to the application filed on February 28, 2025 in which claims 1 – 20 are presented for examination.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 9, and 17 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/29/2026 and 7/30/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 2 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of copending Application No. 19/067654 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of 19/067654 is broader than claim 2 of the instant application (and because claim 3 of 19/067654 is broader than claim 2 of the instant application).
Claims 3, 4, 6, and 7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 5, 7, and 8 of copending Application No. 19/067654 (reference application), since claims 3, 4, 6, and 7 of the instant application are identical to claims 4, 5, 7, and 8 of 19/067654.
Claim 18 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of copending Application No. 19/067654 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of 19/067654 is broader than claim 18 of the instant application.
Claims 19 and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 17 of copending Application No. 19/067654 (reference application), since claims 19 and 20 of the instant application are identical to claims 16 and 17 of 19/067654.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
19/067654
19/067670 (instant application)
1. A processing system, comprising: a first single instruction multiple data (SIMD) coprocessor comprising a plurality of SIMD registers,
each of the plurality of SIMD registers including a plurality
of SIMD lanes in data communication with a memory,
wherein the first SIMD coprocessor is configured to: receive an instruction included in a first instruction set architecture; and
execute the instruction independent of a cross-lane operation occurring between the plurality of SIMD lanes.
3. The processing system of claim 1, further comprising: a second SIMD coprocessor configured to be in data communication with the memory, the second SIMD coprocessor further configured to execute an instruction included in a second instruction set architecture to perform cross-SIMD lane operations.
1. A processing system, comprising: a first single instruction multiple data (SIMD) coprocessor including a first plurality of SIMD registers,
each of the first plurality of SIMD registers including a first plurality of SIMD lanes,
the first SIMD coprocessor configured to: move data from a SIMD register of the plurality of SIMD registers to a memory independent of a cross-lane operation occurring between the first plurality of SIMD lanes of the SIMD register;
a second SIMD coprocessor including a second plurality of SIMD registers, each of the second plurality of SIMD registers including a second plurality of SIMD lanes, the second SIMD coprocessor configured to: move the data from the memory to a SIMD register of the second plurality of SIMD registers;
perform movement operations on the data that involve cross-lane operations between the second plurality of SIMD lanes of the SIMD register.
2. The processing system of claim 1, wherein: to move the data to the memory, the first SIMD coprocessor is configured to execute an instruction included in a first instruction set architecture; and
to perform movement operations on the data, the second SIMD coprocessor is configured to execute one or more instructions included in a second instruction set architecture that is different from the first instruction set architecture.
4. The processing system of claim 3, wherein the first instruction set architecture comprises lane-wise only instructions.
5. The processing system of claim 3, wherein the second instruction set architecture comprises cross-lane instructions.
7. The processing system of claim 3, wherein the second SIMD coprocessor is configured with limited access rights to one or more SIMD registers of the plurality of SIMD registers of the first SIMD coprocessor.
8. The processing system of claim 7, wherein the limited access rights include read-only access or no read/write access.
3. The processing system of claim 2, wherein the first instruction set architecture includes lane-wise only instruction[s].
4. The processing system of claim 2, wherein the second instruction set architecture includes cross-lane instructions.
The processing system of claim 1, wherein the second SIMD coprocessor is configured with limited access rights to the first plurality of SIMD registers of the first SIMD coprocessor.
7. The processing system of claim 6, wherein the limited access rights include read-only access or no read/write access.
14. An apparatus, comprising: a first single instruction multiple data (SIMD) coprocessor comprising a plurality of SIMD registers, each of the plurality of SIMD registers including a plurality of SIMD lanes in data communication with a memory; and
a second SIMD coprocessor configured to be in data communication with the memory,
the second SIMD coprocessor further configured to execute an instruction included in a second instruction set architecture to perform cross-SIMD lane operations, wherein
the first SIMD coprocessor is configured to: receive an instruction included in a first instruction set architecture; and execute the instruction independent of a cross-lane operation occurring between the plurality of SIMD lanes.
17. An apparatus, comprising a first single instruction multiple data (SIMD) coprocessor including a first plurality of SIMD registers, each of the first plurality of SIMD registers including a first plurality of SIMD lanes,
the first SIMD coprocessor configured to: move data from a SIMD register of the plurality of SIMD registers to a memory independent of a cross-lane operation occurring between the first plurality of SIMD lanes of the SIMD register;
a second SIMD coprocessor including a second plurality of SIMD registers, each of the second plurality of SIMD registers including a second plurality of SIMD lanes,
the second SIMD coprocessor configured to: move the data from the memory to a SIMD register of the second plurality of SIMD registers;
perform movement operations on the data that involve cross-lane operations between the second plurality of SIMD lanes of the SIMD register.
18. The apparatus of claim 17, wherein: to move the data to the memory, the first SIMD coprocessor is configured to execute an instruction included in a first instruction set architecture; and
to perform movement operations on the data, the second SIMD coprocessor is configured to execute one or more instructions included in a second instruction set architecture that is different from the first instruction set architecture.
16. The apparatus of claim 14, wherein the first instruction set architecture comprises lane-wise only instructions.
17. The apparatus of claim 16, wherein the second instruction set architecture comprises cross-lane instructions.
19. The apparatus of claim 18, wherein the first instruction set architecture includes lane-wise only instruction.
20. The apparatus of claim 19, wherein the second instruction set architecture includes cross-lane instructions.
Drawings
The drawings are objected to because Fig. 6 step 604 refers to ‘a SIMD’ twice. The examiner recommends amending step 604 to refer to ‘an SIMD.’ Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because the abstract refers to ‘a SIMD.’ The examiner recommends amending the abstract to refer to ‘an SIMD.’ A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities: there are many instances of ‘a SIMD’ throughout the specification. The examiner recommends amending each instance of ‘a SIMD’ to ‘an SIMD.’ The paragraphs with ‘a SIMD’ are [0004], [0005], [0006], [0010], [0019], [0023], [0024], [0027], [0029], [0050], [0072], [0080], and [0088].
Appropriate correction is required.
Claim Objections
Claims 1 – 20 are objected to because of the following informalities: Independent claims 1, 9, and 17 all refer to ‘a SIMD’ (claim 1 lines 5 and 11, claim 9 line 7, and claim 17 lines 5 and 11). The examiner recommends amending each instance of ‘a SIMD’ to ‘an SIMD.’ All other claims inherit this objection based on their dependencies. Appropriate correction is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over “Qualcomm Hexagon V73 HVX Programmer’s Reference Manual” (hereinafter referred to as Qualcomm) (from Applicant’s IDS) in view of Nagarajan et al., U.S. Patent Application 2023/0153115 (hereinafter referred to as Nagarajan) (from Applicant’s IDS).
Referring to claim 1, Qualcomm discloses “A processing system” (Figure 1-1), “comprising: a first” core “including a first plurality of” “registers” (Figure 1-1 core with R0-R31), “the first” core “configured to: move data from a” “register of the plurality of” “registers to a memory” (Figure 1-1 core to L2/TCM memory); “a” “SIMD coprocessor including a” “plurality of SIMD registers, each of the” “plurality of SIMD registers including a” “plurality of SIMD lanes” (Figure 1-1 SIMD coprocessor with vector registers V0-V31 and section 1.2.4 HVX vector registers partitioned into lanes that operate in SIMD fashion), the “SIMD coprocessor configured to: move the data from the memory to a SIMD register of the” “plurality of SIMD registers” (5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions. Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space); “perform movement operations on the data that involve cross-lane operations between the” “plurality of SIMD lanes of the SIMD register” (page 218 'Vector shuffle and deal cross-lane').
Qualcomm’s system teaches a Hexagon core and an SIMD coprocessor both connected to memory L2 TCM (Figures 1-1 and 1-3).
Qualcomm does not appear to explicitly disclose “A processing system, comprising: a first single instruction multiple data (SIMD) coprocessor including a first plurality of SIMD registers, each of the first plurality of SIMD registers including a first plurality of SIMD lanes, the first SIMD coprocessor configured to: move data from a SIMD register of the plurality of SIMD registers to a memory independent of a cross-lane operation occurring between the first plurality of SIMD lanes of the SIMD register; a second SIMD coprocessor including a second plurality of SIMD registers, each of the second plurality of SIMD registers including a second plurality of SIMD lanes, the second SIMD coprocessor configured to: move the data from the memory to a SIMD register of the second plurality of SIMD registers; perform movement operations on the data that involve cross-lane operations between the second plurality of SIMD lanes of the SIMD register.”
However, Nagarajan discloses another system comprising “a first single instruction multiple data (SIMD) coprocessor including a first plurality of SIMD registers, each of the first plurality of SIMD registers including a first plurality of SIMD lanes” (Fig. 1 two co-processors 103/104 and memory 107. [0035] "a cross-lane processing unit (XPU)" and "configuring individual operations performed by processing cells and arranging crossbars as a stacked network in the XPU. The XPU operates across values of multiple SIMD data processing lanes. The XPU can be implemented as part of a co-processor configured for SIMD parallel processing." [0042] each data processing lane can include one or more registers), “the first SIMD coprocessor configured to: move data from a SIMD register of the plurality of SIMD registers to a memory” ([0072] XPU registers used to store and retrieve data. Fig. 1 and [0050] the high bandwidth memory 107 servicing one or both of the co-processors 103 and 104. [0058] XPU receives instructions, scatter/gather controller 222 receives data and controls what data is passed to memory 206).
As for the limitation of moving data from an SIMD register to memory “independent of a cross-lane operation occurring between the first plurality of SIMD lanes of the SIMD register,” both Qualcomm and Nagarajan teach cross-lane operations and separate, independent memory access (Qualcomm section 5.1.2 shows an ‘aligned memory (.tmp/.new)’ instruction, which uses resources of load and store only, while other instructions utilize permute and shift resources. Nagarajan Fig. 7 and [0035] cross-lane processing unit XPU can be configured to perform different operations in response to input signals and arranging crossbars. [0058] A scatter/gather controller 222 of the tile 102 can receive incoming data and control what data is passed in the memory 206 through a memory scheduler 214).
Qualcomm and Nagarajan are analogous art because they are from the same field of endeavor, which is SIMD co-processors and lanes.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Qualcomm and Nagarajan before him or her, to modify the teachings of Qualcomm to include the teachings of Nagarajan so that two SIMD co-processors, both with SIMD registers and SIMD lanes move data to/from a memory while implementing cross-lane processing when necessary.
The motivation for doing so would have been to provide a means for optimizing performance of data-dependent/input-dependent operations (as described by Nagarajan at [0036]).
Therefore, it would have been obvious to combine Nagarajan with Qualcomm to obtain the invention as specified in the instant claim.
As per claim 2, Qualcomm discloses “to move the data to the memory,” a core “is configured to execute an instruction included in a first instruction set architecture” (Figure 1-1 core to L2/TCM memory. Introduction - "This document describes the Qualcomm Hexagon Vector eXtensions (HVX) instruction set architecture. These extensions are implemented in an optional coprocessor." This implies that the core utilizes a different instruction set architecture without extensions); “and to perform movement operations on the data, the” “SIMD coprocessor is configured to execute one or more instructions included in a second instruction set architecture that is different from the first instruction set architecture ” (Introduction - "This document describes the Qualcomm Hexagon Vector eXtensions (HVX) instruction set architecture. These extensions are implemented in an optional coprocessor." This implies that the core utilizes a different instruction set architecture without extensions. 5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions. Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space).
As above, Naragajan teaches “to move the data to the memory, the first SIMD coprocessor” (Fig. 1 two SIMD co-processors and [0057] ISA with instructions).
Qualcomm and Nagarajan are analogous art because they are from the same field of endeavor, which is SIMD co-processors and lanes.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Qualcomm and Nagarajan before him or her, to modify the teachings of Qualcomm to include the teachings of Nagarajan so that two SIMD co-processors, both with SIMD registers and SIMD lanes move data to/from a memory while implementing cross-lane processing when necessary.
The motivation for doing so would have been to provide a means for optimizing performance of data-dependent/input-dependent operations (as described by Nagarajan at [0036]).
Therefore, it would have been obvious to combine Nagarajan with Qualcomm to obtain the invention as specified in the instant claim.
As per claim 3, Qualcomm discloses “the first instruction set architecture includes lane-wise only instruction” (section 5.1.2 shows an ‘aligned memory (.tmp/.new)’ instruction, which uses resources of load and store only). Also, Nagarajan discloses “the first instruction set architecture includes lane-wise only instruction” ([0062] “The crossbar is configured to permute input values from each processing cell in the same stage according to a fixed pattern. The pattern depends on the composed operation the XPU is currently configured to perform and does not necessarily cause the crossbar to permute every processing cell output. In other words, some processing cell outputs may bypass the crossbar and proceed to the next stage along the same processing lane”).
As per claim 4, Qualcomm discloses “the second instruction set architecture includes cross-lane instructions” (page 218 'Vector shuffle and deal cross-lane').
As per claim 5, Qualcomm discloses load and store instructions that involve memory access and moving data to and from memory (5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions. Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space). Also, as above, Nagarajan discloses two SIMD co-processors (Fig. 1 two co-processors 103/104 and memory 107) as well as moving data from SIMD co-processor to memory and moving data from memory to SIMD co-processor ([0072] XPU registers used to store and retrieve data. Fig. 1 and [0050] the high bandwidth memory 107 servicing one or both of the co-processors 103 and 104. [0058] XPU receives instructions, scatter/gather controller 222 receives data and controls what data is passed to memory 206).
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize data movement operations so that “subsequent to performing the movement operations on the data” (Qualcomm’s section 5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions. Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space), “the second SIMD coprocessor is configured to move the data to the memory; and the first SIMD coprocessor is configured to move the data from the memory to the SIMD register of the first plurality of SIMD registers” (Nagarajan’s [0072] XPU registers used to store and retrieve data. Fig. 1 and [0050] the high bandwidth memory 107 servicing one or both of the co-processors 103 and 104. [0058] XPU receives instructions, scatter/gather controller 222 receives data and controls what data is passed to memory 206).
Referring to claim 9, Qualcomm discloses “A method performable by a processing system comprising a” core “and a” “single instruction multiple data (SIMD) coprocessor” (Figure 1-1), “the method comprising: moving, by the” core, “data from a first” “register of the” core “to a first segment of a memory” (Figure 1-1 core with R0-R31 and core to L2/TCM memory); “retrieving, by the” “SIMD coprocessor, the data from the first segment of the memory and storing the data in a first SIMD lane of a SIMD register of the” “SIMD coprocessor that supports intra-SIMD data movement” (Figure 1-1 SIMD coprocessor with vector registers V0-V31 and section 1.2.4 HVX vector registers partitioned into lanes that operate in SIMD fashion. 5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions with permute and shift. Also page 218 'Vector shuffle and deal cross-lane.' Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space); “executing, by the” “SIMD coprocessor, one or more instructions to move the data from the first SIMD lane of the SIMD register of the” “SIMD coprocessor to a second SIMD lane of the SIMD register of the” “SIMD coprocessor” (5.1.2 'unaligned memory access' and 'aligned memory' show load and store instructions with permute and shift. Also page 218 'Vector shuffle and deal cross-lane'); “loading, by the” “SIMD coprocessor, the data stored in the second SIMD lane of the SIMD register of the” “SIMD coprocessor onto a second segment of the memory” (Section 3.4 HVX is designed to work with L2 cache, L2TCM, or VTCM. Table 4-1 event 281 TCM load access for HVX to load from the L2 TCM space. Section 5.1.2 shows an ‘aligned memory (.tmp/.new)’ instruction, which uses resources of load and store only); “and retrieving, by the” core, “the data stored on the second segment of the memory and storing the data on a” register of the core (Figure 1-1 Hexagon core with registers R0-R31 and bidirectional connection with L2 TCM memory).
As above, Qualcomm does not appear to explicitly disclose “A method performable by a processing system comprising a first single instruction multiple data (SIMD) coprocessor and a second single instruction multiple data (SIMD) coprocessor, the method comprising: moving, by the first SIMD coprocessor, data from a first SIMD lane of a lane-wise SIMD register of the first SIMD coprocessor to a first segment of a memory; retrieving, by the second SIMD coprocessor, the data from the first segment of the memory and storing the data in a first SIMD lane of a SIMD register of the second SIMD coprocessor that supports intra-SIMD data movement;
executing, by the second SIMD coprocessor, one or more instructions to move
the data from the first SIMD lane of the SIMD register of the second SIMD coprocessor
to a second SIMD lane of the SIMD register of the second SIMD coprocessor;
loading, by the second SIMD coprocessor, the data stored in the second SIMD
lane of the SIMD register of the second SIMD coprocessor onto a second segment of
the memory; and retrieving, by the first SIMD coprocessor, the data stored on the second segment of the memory and storing the data on a second SIMD lane of the lane-wise SIMD register of the first SIMD coprocessor.”
However, Nagarajan discloses another system comprising “a first single instruction multiple data (SIMD) coprocessor and a second single instruction multiple data (SIMD) coprocessor” (Fig. 1 two co-processors 103/104 and memory 107. [0035] "a cross-lane processing unit (XPU)" and "configuring individual operations performed by processing cells and arranging crossbars as a stacked network in the XPU. The XPU operates across values of multiple SIMD data processing lanes. The XPU can be implemented as part of a co-processor configured for SIMD parallel processing." [0042] each data processing lane can include one or more registers), “the method comprising: moving, by the first SIMD coprocessor, data from a first SIMD lane of a lane-wise SIMD register of the first SIMD coprocessor to a first segment of a memory” ([0072] XPU registers used to store and retrieve data. Fig. 1 and [0050] the high bandwidth memory 107 servicing one or both of the co-processors 103 and 104. [0058] XPU receives instructions, scatter/gather controller 222 receives data and controls what data is passed to memory 206. Again, [0035] “The XPU operates across values of multiple SIMD data processing lanes. The XPU can be implemented as part of a co-processor configured for SIMD parallel processing." [0042] each data processing lane can include one or more registers. Nagarajan also teaches lane-wise SIMD registers at [0062] “The crossbar is configured to permute input values from each processing cell in the same stage according to a fixed pattern. The pattern depends on the composed operation the XPU is currently configured to perform and does not necessarily cause the crossbar to permute every processing cell output. In other words, some processing cell outputs may bypass the crossbar and proceed to the next stage along the same processing lane”); “and retrieving, by the first SIMD coprocessor, the data stored on the second segment of the memory and storing the data on a second SIMD lane of the lane-wise SIMD register of the first SIMD coprocessor” ([0072] XPU registers used to store and retrieve data. Fig. 1 and [0050] the high bandwidth memory 107 servicing one or both of the co-processors 103 and 104. [0058] XPU receives instructions, scatter/gather controller 222 receives data and controls what data is passed to memory 206. [0042] each data processing lane can include one or more registers).
Qualcomm and Nagarajan are analogous art because they are from the same field of endeavor, which is SIMD co-processors and lanes.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Qualcomm and Nagarajan before him or her, to modify the teachings of Qualcomm to include the teachings of Nagarajan so that two SIMD co-processors, both with SIMD registers and SIMD lanes move data to/from a memory while implementing cross-lane processing when necessary.
The motivation for doing so would have been to provide a means for optimizing performance of data-dependent/input-dependent operations (as described by Nagarajan at [0036]).
Therefore, it would have been obvious to combine Nagarajan with Qualcomm to obtain the invention as specified in the instant claim.
Note, claim 10 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 10.
Note, claim 11 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 11.
Note, claim 12 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 12.
Note, claim 13 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 13.
Referring to claim 17, claim 1 recites the corresponding limitations as that of claim 17. Therefore, the rejection of claim 1 applies to claim 17.
Note, claim 18 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 18.
Note, claim 19 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 19.
Note, claim 20 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 20.
Allowable Subject Matter
Claims 6 – 8 and 14 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 20220129269 teaches configuring SIMD register lanes.
U.S. Patent Application 20250307348 teaches a cross-lane processing unit and a vector processing unit that can be configured for performing element-wise operations on data.
U.S. Patent Application 20220206791 teaches both non-cross-lane instructions and cross-lane instructions as well as vector memory instructions that transfer data from/to memory in a data element-wise fashion.
U.S. Patent Applications 20230153116, 20230161592, 20240211264, 20250251940 and Patents 11972263, 12353887, 12468535 are also to Nagarajan, with similar teachings.
U.S. Patent Application 20260259739 is another application of Applicant.
Machine Translation of German Patent Application DE 102025100072 A1 teaches configuring SIMD register lanes, as well as intra-lane and inter-lane swaps.
‘VeGen: A Vectorizer Generator for SIMD and Beyond’ by Yishen Chen et al. teaches lane level parallelism and applying operations element-wise.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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