DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 14 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 2024/0339077).
Regarding claim 1, Li teaches a pixel circuit (Fig. 2), comprising:
a drive module (Fig. 2: drive circuit 02), wherein the drive module comprises a first transistor (Fig. 2: first drive transistor T3-1) and a second transistor (Fig. 2: second drive transistor T3-2) connected in parallel, a first terminal (Fig. 2: lower terminal of first drive transistor T3-1) of the first transistor and a first terminal (Fig. 2: lower terminal of second drive transistor T3-2) of the second transistor are connected to form a first end (Fig. 2: node N3) of the drive module, a second terminal (Fig. 2: upper terminal of first drive transistor T3-1) of the first transistor and a second terminal (Fig. 2: upper terminal of second drive transistor T3-2) of the second transistor are connected to form a second end (Fig. 2: node N2) of the drive module, a first gate (Fig. 2: gate of first drive transistor T3-1) of the first transistor and a second gate (Fig. 2: gate of second drive transistor T3-2) of the second transistor are connected to form a control end (Fig. 2: node N1) of the drive module, and a subthreshold swing of the first transistor is greater than a subthreshold swing of the second transistor ([0086]: “the subthreshold swing ss of one of the first drive transistor T3-1 and the second drive transistor T3-2 is greater than the subthreshold swing ss of the other one of the first drive transistor T3-1 and the second drive transistor T3-2”; [0089]: “The subthreshold swing ss of the first drive transistor T3-1 is greater than the subthreshold swing ss of the second drive transistor T3-2”).
Regarding claim 5, Li teaches the pixel circuit according to claim 1, further comprising a compensation module (Fig. 2: compensation control sub-circuit 013), wherein the compensation module is connected between the control end (Fig. 2: node N1) and the first end (Fig. 2: node N2) of the drive module and is configured to transmit a data voltage of the first end of the drive module to the control end of the drive module in a data writing stage (Fig. 2: in data writing stage, i.e., when “Gate” signal is “on” signal, Vdata is transmitted to Node N2 and N3; because T2 is turned on in the stage, Vdata at node N3 is transmitted to node N1) and compensate for a threshold voltage of the drive module in a compensation stage (Fig. 2: compensation stage corresponds to a stage when “Gate” signal is “on” signal).
Regarding claim 14, Li teaches a method for driving a pixel circuit, which is applied to the pixel circuit according to claim 1, the method comprising:
generating, by both the first transistor and the second transistor, drive currents (Figs. 2-3: driving current by drive circuit 02 to light-emitting element L1) in a light emitting stage (Fig. 2: light emitting stage corresponds to a stage when “EM” signal is “on” signal), to drive a light emitting module to emit light, wherein
during display of a first gray scale (Fig. 3: a first gray scale corresponds to data voltage smaller than voltage V at which IV characteristic curves of the first and two drive transistors cross each other), the drive current generated in the first transistor is greater than the drive current generated in the second transistor, during display of a second gray scale (Fig. 3: a second gray scale corresponds to data voltage larger than voltage V at which IV characteristic curves of the first and two drive transistors cross each other), the drive current generated in the first transistor is less than the drive current generated in the second transistor, and a gray scale value of the first gray scale is less than a gray scale value of the second gray scale.
Regarding claim 16, Li further teaches a display panel ([0002]; [0027]; Fig. 5; Fig. 15), comprising the pixel circuit according to claim 1.
Regarding claim 17, Li further teaches the display panel according to claim 1, wherein a control end of a first reset module (Fig. 2: “Reset” signal terminal of first reset sub-circuit 011) and a control end of a second reset module (Fig. 2: “Reset” signal terminal of second reset sub-circuit 016) are connected to a first scan signal (Fig. 2: “Reset” signal);
a control end of a compensation module (Fig. 2: gate terminal of compensation control sub-circuit 013) is connected to a second scan signal (Fig. 2: “Gate” signal);
a control end of a data writing module (Fig. 2: gate terminal of data writing sub-circuit 012) is connected to a third scan signal (Fig. 2: “Gate” signal);
a control end of a first light-emission control module (Fig. 2: gate terminal of first light emission control sub-circuit 014) is connected to a first light-emission control signal (Fig. 2: “EM” signal); and
a control end of a second light-emission control module (Fig. 2: gate terminal of second light emission control sub-circuit 015) is connected to a second light- emission control signal (Fig. 2: “EM” signal).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2024/0339077) in view of Zhang (US Patent No. 10,916,197).
Regarding claim 2, Li does not further teach the pixel circuit according to claim 1, wherein the first transistor further comprises a third gate disposed opposite the first gate with respect to a channel of the first transistor; or
the second transistor further comprises a fourth gate disposed opposite the second gate with respect to a channel of the second transistor.
The differentiating feature indicates at least one of the first transistor and the second transistor is of a double-gate structure. However, it is not new in the related art using a dual-gate structure for a driving transistor.
Zhang, for instance, teaches in Fig. 6 and Col. 3, ll. 21-25 using a dual-gate structure for a driving transistor, i.e., the top gate 605 disposed opposite the bottom gate 601 with respect to a channel 603 of the first transistor (drive transistor T1 in Fig. 1).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Li with the technique of Zhang forming both the first transistor and the second transistor in the form of a double-gate structure to achieve respectively regulating channels with the bottom gate and the top gate to realize the dynamic adjustment of the threshold voltage of the driving transistor for effectively broadening the range of the compensation of the threshold voltage (Col. 3, ll. 27-36).
Regarding claim 3, Li does not further teach the pixel circuit according to claim 1, wherein the first transistor further comprises a third gate disposed opposite the first gate with respect to a channel of the first transistor, and the second transistor further comprises a fourth gate disposed opposite the second gate with respect to a channel of the second transistor.
The differentiating features indicate the first transistor and the second transistor are of a double-gate structure. However, it is not new in the related art using a dual-gate structure for a driving transistor.
Zhang, for instance, teaches in Fig. 6 and Col. 3, ll. 21-25 using a dual-gate structure for a driving transistor, i.e., the top gate 605 disposed opposite the bottom gate 601 with respect to a channel 603 of the first transistor (drive transistor T1 in Fig. 1).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Li with the technique of Zhang forming both the first transistor and the second transistor in the form of a double-gate structure to achieve respectively regulating channels with the bottom gate and the top gate to realize the dynamic adjustment of the threshold voltage of the driving transistor for effectively broadening the range of the compensation of the threshold voltage (Col. 3, ll. 27-36).
Allowable Subject Matter
Claims 4, 6-13, 15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4: the third gate of the first transistor and the fourth gate of the second transistor are arranged on different layers, i.e., “the third gate of the first transistor is a top gate of the first transistor” and “the fourth gate of the second transistor is a bottom gate of the second transistor”.
Claim 6: relationships between channel-width and channel-length products of the first to third transistors, i.e., “Al < A3, or A2 < A3”.
Claim 7: presence and structure of coupling module in the pixel circuit.
Claim 8: presence and structures of three different reset modules in the pixel circuit.
Claim 15: relationships between different stages of the pixel circuit.
Claims 18-20: presence and structure of a third reset module in the pixel cirucit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2020/0302860 by Kim et al. discloses in Fig. 4 driving transistor DT is a dual transistor including a first driving transistor DT1 and a second driving transistor DT2.
CN 116844473 A by Li et al. discloses in Figs. 1-2 first driving transistor T1 in drive circuit 100 that includes two driving transistors T1 and T2 includes bottom gate 2064 and top gate 2065.
CN 114999364 B by Yang et al. discloses in Fig. 4 a drive module includes two driving transistors (respectively driving transistor M3-1 and driving transistor M3-2) connected in parallel. Optionally, the width-length ratio of one of the two drive transistors is greater than the width-length ratio of the other of the two drive transistors to achieve better displaying of low-brightness images;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629