Prosecution Insights
Last updated: July 17, 2026
Application No. 19/068,321

MEMORY DEVICE INTERFACE COMMUNICATING WITH SET OF DATA BURSTS CORRESPONDING TO MEMORY DIES VIA DEDICATED PORTIONS FOR COMMAND PROCESSING

Non-Final OA §DP
Filed
Mar 03, 2025
Priority
Oct 27, 2020 — continuation of 11/347,663 +2 more
Examiner
PEYTON, TAMMARA R
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Lodestar Licensing Group LLC
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
875 granted / 963 resolved
+35.9% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
978
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
75.2%
+35.2% vs TC avg
§102
8.7%
-31.3% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 963 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,347,663. Instant Application 19/068,321 Claim 1, US Patent 11,347,663 A system, comprising: a plurality of memory dies; A method comprising: communicating, by a processing device of a controller of a memory sub-system, a memory device interface coupled to the plurality of memory dies, the memory device interface including a command interface portion and a data burst interface portion, the command interface portion including an address latch enable pin and a command latch enable pin, wherein the command interface portion is configured to communicate memory device commands and the data burst interface portion is configured to communicate data bursts, a set of memory commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device; and causing communication of a set of data bursts corresponding to the set of memory commands to the one or more memory dies via a second portion of the interface wherein the command interface portion and the data burst interface portion are separate from one another; and a memory sub-system controller coupled to the memory device interface and configured to use the command interface portion to communicate one or more commands in parallel with communicating one or more data bursts via the data burst interface portion to allow concurrent command and data traffic. wherein one or more of the set of memory commands are communicated via the first portion of the interface concurrently with one or more of the set of data bursts communicated via the second portion of the interface. Claim 1 of US Patent 11,347,663 teaches some of the elements of the claim 2 of 19/068,321. Especially the claims limitation from US 11,347,663 like “…one or more of the set of memory commands are communicated via the first portion of the interface concurrently with one or more of the set of data bursts communicated via the second portion of the interface.” Claims 2-20 from 19/068,321 is similar to claims 1-20 of US 11, 347,663, therein claims 2-21, therein a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome nonstatutory double patenting rejection. RELEVENT ART CITED BY THE EXAMINER The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). The sited prior art Mai et al., (US 10,783,968) teaches a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. (Figs. 1 and 2, Abstract) Conclusion The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tammara Peyton whose telephone number is (571) 272-4157. The examiner can normally be reached between 8:30- 6:00 from Monday to Thursday, (I am off every first Friday), and 7:30- 4:00 every second Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Henry Tsai can be reached on (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Any inquiry of a general nature of relating to the status of this application should be directed to the Group receptionist whose telephone number is (571) 272- 2100. /Tammara R Peyton/ Primary Examiner, Art Unit 2184 June 13, 2026
Read full office action

Prosecution Timeline

Mar 03, 2025
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+6.0%)
2y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 963 resolved cases by this examiner. Grant probability derived from career allowance rate.

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