DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/03/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 14 recites the limitation "the top intermediate layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 8-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu (US 2023/0039444 A1).
Regarding claim 1, Wu teaches an antenna in package (AIP), comprising:
a top side package substrate (Fig. 2, 20, [0048] top antenna package 20) including a top metal layer including an antenna (Fig. 2, 220, [0045] a radiative antenna element 220) and a bottom metal layer (214, [0045] conductive trace 214) separated from the top metal layer (220) by a dielectric layer (210, [0044] 210, a dielectric substrate) that includes filled vias (212, [0043] through-holes 212 to route signals) for electrically connecting the top metal layer to the bottom metal layer (220-212-214), the bottom metal layer including a plurality of contact pads including a first contact pad and a second contact pad (Fig. 2, 214, two pads are shown);
an integrated circuit (IC) die (Fig. 2, 30, [0030] semiconductor chip 30) comprising a substrate including a top side semiconductor surface including circuitry having a plurality of bond pads thereon electrically connected to nodes in the circuitry (Fig. 2, [0048] conductive elements 312);
a bottom side package substrate (Fig. 2, [0040] bottom package 10) including a bottom side and a top side having a plurality of metal pads including a first metal pad and a second metal pad, the first metal pad (Fig. 2, metal pad for 240) for electrically coupling to vertical connectors (240), and the second metal pad for electrically coupling to the plurality of bond pads (Fig. 2, 124 for 312);
the vertical connectors (Fig. 2, 240) including at least a first vertical connector between the first metal pad and the first contact pad (214) for providing a transmission line for the antenna (220);
wherein there is an air gap including between the first vertical connector and the antenna (Fig. 2, gap between 240 and 20, [0049] see the difference between the package 1c and 1b).
Regarding claim 2, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, wherein the bottom side package substrate further comprises a ball grid array (BGA) on the bottom side of the bottom side package substrate (Fig. 2, 140).
Regarding claim 3, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, wherein the IC die is flipchip attached to the second metal pad ([0012] a flip-chip package, [0073] semiconductor chip 30, flip-chip techniques).
Regarding claim 4, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, wherein the IC die is wirebonded by wirebonds between the plurality of bond pads and the second metal pad ([0012] wire-bond type package), and wherein the IC die is part of a packaged device which includes an encapsulation layer for the IC die ([0013] encapsulating the first electronic component).
Regarding claim 8, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, further comprising an application printed circuit board (PCB), wherein the AIP is assembled on a top surface of the PCB ([0042] further connection to a printed circuit board or a main board).
Regarding claim 9, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, wherein the antenna comprises a millimeter wave antenna ([0045] millimeter-wave).
Regarding claim 10, all the limitations of claim 1 are taught by Wu.
Wu further teaches the AIP, wherein the IC die comprises a radio frequency (RF) die ([0045] RF wireless signals).
Claims 12 and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chuang (US 2021/0343665 A1).
Regarding claim 12, Chuang teaches An antenna in package (AIP), comprising:
an integrated circuit (IC) die (Fig. 2C, 109) comprising a substrate including a top side semiconductor surface including circuitry having a plurality of bond pads electrically connected to nodes in the circuitry (109 having bond pads as shown in Fig. 2C connecting to redistribution layer 105, [0020]);
a package substrate (Fig. 2C, 137, 127, 105) including the IC die (109) mounted with a top side up (a top side of 109 is up), wherein the IC die is completely embedded therein ([0056] encapsulant 127), the package substrate comprising a top layer including a top dielectric layer (Fig. 2B, 153, [0074] passivation layer 153) and a top metal layer including an antenna ([0032] an first upper antenna layer 151), and a bottom layer including a bottom dielectric layer ([0074] passivation layer 145) and a bottom metal layer (Fig. 2B, 143) including a plurality of contact pads including a first contact pad a second contact pad (contact pads above 147), and a plurality of filled vias (vias 149, [0074] feeding element 149);
the plurality of bond pads electrically coupled by a via-comprising die connection (Fig. 2C, Fig. 2B, 149) including at least one of the plurality of filled vias (Fig. 2B, 149) for connecting to at least one of the top metal layer and the bottom metal layer (Fig. 2B, 149), and
a plurality of metal pillars including a first metal pillar electrically coupled between the first contact pad and the antenna, and a second metal pillar (Figs. 2B, 2C, 147),
wherein at least one of the plurality of filled vias is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna (Fig. 2B, 2C, 147 connects to the filled via 149).
Regarding claim 15, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, wherein the dielectric layer comprises a composite organic material comprising an epoxy ([0031] the underfill material 115 is a liquid epoxy).
Regarding claim 16, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, further comprising an application printed circuit board (PCB), wherein the AIP is assembled on a top surface of the PCB (Fig. 2C, [0062] external connections 157).
Regarding claim 17, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, wherein the antenna comprises a millimeter wave antenna ([0010]).
Regarding claim 18, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, wherein the IC die comprises a radio frequency (RF) die ([0010]).
Regarding claim 19, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, wherein a width and a line spacing for the top metal layer and for the bottom metal layer includes a dimension that is less than or equal to 10 μm ([0018] 5 μm).
Regarding claim 20, all the limitations of claim 1 are taught by Chuang.
Chuang further teaches the AIP, wherein a thickness of the AIP is less than or equal to 600 μm ([0062] height about 350 μm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0039444 A1) in view of Hsu (US 2020/0243464 A1).
Regarding claim 5, all the limitations of claim 4 are taught by Wu.
Wu does not explicitly teach the AIP, wherein the bottom side package substrate provides a metal heat slug positioned beneath a bottom side of the IC die.
Hsu teaches an AIP, wherein the bottom side package substrate provides a metal heat slug positioned beneath a bottom side of the IC die (Fig. 2, 30, [0046] a metal thermal interface layer 30).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the thermal interface layer of Hsu to the IC die of Wu in order to provide an efficient heat conduction from the IC (Hsu, [0004]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0039444 A1) in view of Chuang (US 2021/0343665A1).
Regarding claim 6, all the limitations of claim 1 are taught by Wu.
Wu does not explicitly teach the AIP, wherein the dielectric layer comprises a composite organic material comprising an epoxy.
Chuang teaches an AIP wherein a dielectric layer comprises a composite organic material comprising an epoxy (Fig. 2A, 115, [0031] underfill material 115, epoxy).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the underfill of Chuang to the teachings of Wu in order to cushion, support and protect the semiconductor chip of Wu (Chuang, [0031]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0039444 A1).
Regarding claim 7, all the limitations of claim 1 are taught by Wu.
Wu does not explicitly teach the AIP, wherein the vertical connectors (Fig. 2, 240, solder balls) each comprise a metal pillar.
However, Wu further teaches a conductive element such as a solder bump, solder ball, or a metal bump/pillar may be formed on a dielectric layer for connections ([0067], Fig. 12, 640).
Therefore it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of claimed invention to replace the solder ball 240 of Fig. 2 of Wu with a metal pillar to form connections on dielectric layer/substrate because Applicant has not disclosed that a metal pillar provides an advantage, is used for a particular purpose, or solves a stated problem over a solder ball and Wu suggested a connection on a dielectric layer can be formed by any of a solder bump, solder ball, or a metal bump/pillar (Wu, [0067]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2023/0039444 A1) in view of Cheah (US 2021/0384130 A1).
Regarding claim 11, all the limitations of claim 1 are taught by Wu.
Wu does not explicitly teach the AIP, wherein a width and a line spacing for the top metal layer and for the bottom metal layer includes a dimension that is less than or equal to 10 μm.
Cheah teaches an AIP, wherein a width and a line spacing for the top metal layer and for the bottom metal layer includes a dimension that is less than or equal to 10 μm ([0045]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the metal design rule of Cheah to the teachings of Wu in order to achieve a device form-factor miniaturization (Cheah, [0019]).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior arts fail to teach or reasonably suggest an AIP, wherein the package substrate further comprises: a top intermediate layer below the top layer including a top intermediate metal layer and a top intermediate dielectric layer, a bottom intermediate layer below the top intermediate layer including a bottom intermediate metal layer and a bottom intermediate dielectric layer, wherein the bottom intermediate dielectric layer surrounds a majority of a surface area of the IC die, in combination with the other limitations of the claim.
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, the prior arts fail to teach or reasonably suggest an AIP, wherein the via-comprising die connection includes ones of the plurality of filled vias including for electrically connecting at least one of the plurality of bond pads to the top intermediate metal layer and then for connecting the top intermediate metal layer to the top metal layer, and other ones of the plurality of filled vias including for electrically connecting the bond pads to the top intermediate metal layer, with the second metal pillar for electrically connecting to at least one of the plurality of contact pads, in combination with the other limitations of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang Chien (US 2020/0328167 A1) teaches a conductive pillar 140 (Fig. 2, [0045]) and also teaches air gap between two chip packages (Fig. 1J and [0076]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2845
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