Prosecution Insights
Last updated: April 19, 2026
Application No. 19/068,785

SELF-ADDRESSING MEMORY

Non-Final OA §101§DP
Filed
Mar 03, 2025
Examiner
VU, BAI DUC
Art Unit
2163
Tech Center
2100 — Computer Architecture & Software
Assignee
Sadram Inc.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
97%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
588 granted / 747 resolved
+23.7% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
10 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
20.2%
-19.8% vs TC avg
§103
28.0%
-12.0% vs TC avg
§102
16.8%
-23.2% vs TC avg
§112
26.0%
-14.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 747 resolved cases

Office Action

§101 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The instant application having Application No. 19/068,785 filed on 3/3/2025 is presented for examination by the Examiner. Claims 1-21 are currently pending in the present application. Priority As required by M.P.E.P. 201.14(c), acknowledgement is made of Applicant's claim for priority as a CON of 18/384,655 filed on 10/27/2023 now Abandon, which is a CON of 18/225,046 filed on 7/21/2023 now Patent 11,836,128 B1. Drawings The Applicant's drawings filed on 3/3/2025 are acceptable for examination purpose. Information Disclosure Statement As required by M.P.E.P. 609, the Applicant's submission of the Information Disclosure Statement dated 3/3/2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. Examiner Notes With respect to claim 20 which is method claim, the Examiner notes that the claimed functions must, inherently, require a computing processor as taken in view of paragraph [0157] in the Applicant’s instant specification. Therefore, the method of claims 1-19 is a process and that falls within one of the statutory categories of invention under 35 U.S.C. § 101. With respect to claim 21 which is a non-transient operational code stored in a logic layer claim. The Examiner notes that the “logic layer” is interpreted as a hardware physical memory device as taken in view of ¶ 0043 and Figure 1 in the Applicant’s instant disclosure. Therefore, the logic layer of claim 21 is a manufacture and that falls within one of the statutory categories of invention under 35 U.S.C. § 101. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. Claim 1 in this application is given its broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations of claim 1 that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use in each a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is: “a sequencer” in claim 1 (i.e., as describes in the paragraph [0033] lines 6 and 7 of the Applicant’s instant specification). Because this claim limitation is being interpreted under 35 U.S.C. 112(f) it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If Applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), Applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f). Specification Objection The specification is objected to because of the following informalities: The content of Cross-References to Related Applications is missing from the specification. See 37 CFR 1.78 and MPEP § 201.11. Appropriate correction is respectfully required. Abstract Objection The abstract of the disclosure is objected to because it should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. Correction is respectfully required. See MPEP § 608.01(b). Claim Objections Claims 20 and 21 are objected to because of the following informalities: As per claims 20 and 21, the claims recite the feature of “insert a new data set element into the DRAM row or DRAM row-pair” which should be amended as “insert [[a]]the new data set element into the DRAM row or DRAM row-pair”. As per claim 1, 20 and 21; the claims recite “insert the new data set element into the DRAM row or DRAM row-pair” which should be amended or written as “insert the new data set element into the location within the DRAM row or DRAM row-pair”. Appropriate corrections are respectfully required. Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. Claims 1-21 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-21 of prior U.S. Patent No. 11,836,128 B1. This is a statutory double patenting rejection. Allowable Subject Matter Claims 1-21 would be allowable if rewritten or amended to overcome the objections and the rejections as set forth in this Office action. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: After conducting different searches in PE2E - SEARCH, Google Scholar, and ACM Digital Library, it appears that none of prior arts discloses, teaches or fairly suggests the limitations as a whole in the independent claims 1, 20 and 21. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO 0106371 A1 by Seagate Technology LLC teaches a memory system and a manner of operating the memory system are provided. The memory system includes several arrays arranged in groups of columns having a column address, and rows having a row address. Operating the system involves storing blocks of data in the arrays in a way that provides contiguous logical addresses for the blocks of data. A block of data is stored in a row of a group of columns in an array. The row address is incremented and the process repeated until a row limit is reached. Next, the process is repeated with another array until blocks of data have been stored in all rows of a corresponding group of columns in the array. The column address is incremented and the row address reset, and the process repeated until a column limit is reached. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bai D. Vu whose telephone number is (571) 270-1751. The examiner can normally be reached 9:00 - 5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tony Mahmoudi can be reached at (571) 272-4078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAI D VU/Primary Examiner, Art Unit 2163 11/28/2025
Read full office action

Prosecution Timeline

Mar 03, 2025
Application Filed
Nov 29, 2025
Non-Final Rejection — §101, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
97%
With Interview (+18.1%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 747 resolved cases by this examiner. Grant probability derived from career allow rate.

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