DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. In addition, acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 19/068,939, filed on March 3, 2025.
Oath/Declaration
Oath/Declaration as filed on March 3, 2025 is noted by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, and 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, and 2-9 of U.S. Patent No. 11,837,159 in view of Wang et al., U.S. Patent Application Publication 2024/0169906 A1 as English translation of WO/2023004810 (hereinafter Wang). Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 1 of this application and respective claim 1 of U.S. Patent No. 11,837,159:
Instant Application
U.S. Patent No.
11,837,159
Claim 1
Claim 1
A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, and configured to display images including a plurality of frames, each of the plurality of pixels including a pixel circuit and a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, wherein the display panel is configured to operate in a first mode based on a first driving frequency, or in a second mode based on a second driving frequency different from the first driving frequency, wherein images displayed on the display panel include a first image displayed in the first mode, and a second image displayed in the first mode and the second mode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels, and wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode.
A display device comprising: a display panel that includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, the display panel configured to display an image including a plurality of frames; a data driver configured to supply data signals to the plurality of data lines; a gate driver configured to supply gate signals to the plurality of gate lines; and a timing controller configured to control the data driver and the gate driver, wherein the display panel operates in a first mode for displaying the image including the plurality of frames based on a first driving frequency, or in a second mode for displaying the image including the plurality of frames based on a second driving frequency different from the first driving frequency, wherein the image displayed on the display panel operating in the first mode is changed from a first image in which a number of pixels representing a low gray level among the plurality of pixels is equal to or greater than a first threshold value, to a second image in which a number of pixels representing a high gray level among the plurality of pixels is equal to or greater than a second threshold value, wherein at least one frame running after the first image has been displayed among the plurality of frames displaying the second image operates at the second driving frequency based on the second mode, wherein each of the plurality of pixels includes a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels through at least one of the plurality of data lines for a preset time.
Independent claim 1 of the instant application teaches “A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, and configured to display images including a plurality of frames, each of the plurality of pixels including a pixel circuit and a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, wherein the display panel is configured to operate in a first mode based on a first driving frequency, or in a second mode based on a second driving frequency different from the first driving frequency, wherein images displayed on the display panel include a first image displayed in the first mode, and a second image displayed in the first mode and the second mode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels, and wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode.” The U.S. Patent 11,837,159 does not expressly teach: wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode. However, Hwang teaches wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively (T0, N2, N3, N1 FIGS. 67, and 72-3, paragraph[0634] of Wang teaches as shown in FIG. 72, based on at least one embodiment of the pixel circuit shown in FIG. 67, the light emitting element is an organic light emitting diode O1; the compensation control circuit 12 includes a first transistor T1; and the drive circuit 11 includes a drive transistor T0 (i.e., Wang teaches the pixel circuit with a drive transistor having a second electrode, first electrode, and gate electrode connected to second node, third node, and first node)); a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node (T4, D1, T1 FIGS. 67, and 72-74, paragraph[0651] of Wang teaches in the data write phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, both S3 and S4 provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 to the anode of O1, T1 and T4 are turned on to write a data voltage Vdata on D1 to N2, and N1 and N3 are connected, and See also at least paragraphs[0652]-[0656] of Wang (i.e., Wang teaches a fourth transistor that writes a data voltage to the second node, and a first transistor connected having an electrode connected to the third node and an electrode connected to the first node)); a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal (T2, Vi1 FIGS. 67, and 72-74, paragraph[0650] of Wang teaches in the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, both S3 and S4 provide high voltage signals, S1 provides a high voltage signal, and T1 and T2 are turned on to write Vi1 to N1, so that T0 can be turned on at beginning of the data write phase t3, and See also at least paragraphs[0634]-[0649], and [0651]-[0656] of Wang (i.e., Wang teaches second transistor connected to one of the electrodes of the first transistor at the third node, wherein the second transistor is capable of writing a first initialization voltage to the first node)); and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode (T7, Vi2 FIGS. 67, and 72-74, paragraph[0651] of Wang teaches in the data write phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, both S3 and S4 provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 to the anode of O1, T1 and T4 are turned on to write a data voltage Vdata on D1 to N2, and N1 and N3 are connected, and See also at least paragraphs[0634]-[0650], and [0652]-[0656] of Wang (i.e., Wang teaches seventh transistor connected to the anode of an organic light emitting diode of the pixel circuit, wherein the seventh transistor is capable of writing a second initialization voltage to the anode)).
Furthermore, U.S. Patent No. 11,837,159 and Wang are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with suitable circuitry for repairing a disconnection in a signal line. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of U.S. Patent No. 11,837,159 based on Wang wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode. One reason for the modification as taught by Wang is to improve the hysteresis phenomenon of the drive transistor and reduce high and low frequency flicker of the pixel circuit (paragraphs[0587]-[0588] of Wang). In addition, in regard to U.S. Patent No. 11,837,159, it would have been obvious to one of ordinary skill in the art to remove the further limitations “connected to the plurality of data lines and the plurality of gate lines; a data driver configured to supply data signals to the plurality of data lines; a gate driver configured to supply gate signals to the plurality of gate lines; and a timing controller configured to control the data driver and the gate driver; for displaying the image including the plurality of frames; for displaying the image including the plurality of frames; is changed from a first image; through at least one of the plurality of data lines for a preset time”, since at least omitting the further limitation does not prevent the apparatus from functioning properly, and the claim is in “comprising” format indicating other elements could even be added. In addition, dependent claims 11-19 of the instant application are rejected at least based on same above reasoning.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 of U.S. Patent No. 11,837,159. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 20 of this application and respective claim 11 of U.S. Patent No. 11,837,159:
Instant Application
U.S. Patent No.
11,837,159
Claim 20
Claim 11
A method of driving a display device including a display panel, the method comprising: computing gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image or a second image based on a value resulting from the computing, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency.
A method of driving a display device including a display panel, the method comprising: adding gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image representing a low gray level or a second image representing a high gray level based on a value resulting from the adding, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency
Independent claim 20 of the instant application teaches “A method of driving a display device including a display panel, the method comprising: computing gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image or a second image based on a value resulting from the computing, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency.” However, it would have been obvious to one of ordinary skill in the art to remove the further limitations “adding; representing a low gray level; representing a high gray level; the adding” at least since omitting the further limitations does not prevent the method from functioning properly, and the claim is in “comprising” format indicating other elements could be added.
Claims 1, and 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, and 2-9 of U.S. Patent No. 12,272,300 in view of Wang. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 1 of this application and respective claim 1 of U.S. Patent No. 12,272,300:
Instant Application
U.S. Patent No.
12,272,300
Claim 1
Claim 1
A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, and configured to display images including a plurality of frames, each of the plurality of pixels including a pixel circuit and a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, wherein the display panel is configured to operate in a first mode based on a first driving frequency, or in a second mode based on a second driving frequency different from the first driving frequency, wherein images displayed on the display panel include a first image displayed in the first mode, and a second image displayed in the first mode and the second mode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels, and wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode.
A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, and configured to display images including a plurality of frames, each of the plurality of pixels including a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, wherein the display panel operates in a first mode for displaying at least a first image including a plurality of first frames among the plurality of frames based on a first driving frequency, or in a second mode for displaying a second image including a plurality of second frames among the plurality of frames based on a second driving frequency different from the first driving frequency, wherein when the first image displayed on the display panel operating in the first mode is changed to a third image, at least one frame of a plurality of third frames running after the first image has been displayed among the plurality of frames displaying the third image operates at the second driving frequency based on the second mode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels for a preset time.
Independent claim 1 of the instant application teaches “A display device comprising: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, and configured to display images including a plurality of frames, each of the plurality of pixels including a pixel circuit and a light emitting diode including an anode electrode, a cathode electrode, and an emissive layer disposed between the anode electrode and the cathode electrode, wherein the display panel is configured to operate in a first mode based on a first driving frequency, or in a second mode based on a second driving frequency different from the first driving frequency, wherein images displayed on the display panel include a first image displayed in the first mode, and a second image displayed in the first mode and the second mode, and wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels, and wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode.” The U.S. Patent 12,272,300 does not expressly teach: wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode. However, Hwang teaches wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively (T0, N2, N3, N1 FIGS. 67, and 72-3, paragraph[0634] of Wang teaches as shown in FIG. 72, based on at least one embodiment of the pixel circuit shown in FIG. 67, the light emitting element is an organic light emitting diode O1; the compensation control circuit 12 includes a first transistor T1; and the drive circuit 11 includes a drive transistor T0 (i.e., Wang teaches the pixel circuit with a drive transistor having a second electrode, first electrode, and gate electrode connected to second node, third node, and first node)); a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node (T4, D1, T1 FIGS. 67, and 72-74, paragraph[0651] of Wang teaches in the data write phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, both S3 and S4 provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 to the anode of O1, T1 and T4 are turned on to write a data voltage Vdata on D1 to N2, and N1 and N3 are connected, and See also at least paragraphs[0652]-[0656] of Wang (i.e., Wang teaches a fourth transistor that writes a data voltage to the second node, and a first transistor connected having an electrode connected to the third node and an electrode connected to the first node)); a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal (T2, Vi1 FIGS. 67, and 72-74, paragraph[0650] of Wang teaches in the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, both S3 and S4 provide high voltage signals, S1 provides a high voltage signal, and T1 and T2 are turned on to write Vi1 to N1, so that T0 can be turned on at beginning of the data write phase t3, and See also at least paragraphs[0634]-[0649], and [0651]-[0656] of Wang (i.e., Wang teaches second transistor connected to one of the electrodes of the first transistor at the third node, wherein the second transistor is capable of writing a first initialization voltage to the first node)); and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode (T7, Vi2 FIGS. 67, and 72-74, paragraph[0651] of Wang teaches in the data write phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, both S3 and S4 provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 to the anode of O1, T1 and T4 are turned on to write a data voltage Vdata on D1 to N2, and N1 and N3 are connected, and See also at least paragraphs[0634]-[0650], and [0652]-[0656] of Wang (i.e., Wang teaches seventh transistor connected to the anode of an organic light emitting diode of the pixel circuit, wherein the seventh transistor is capable of writing a second initialization voltage to the anode)).
Furthermore, as mentioned above, U.S. Patent No. 12,272,300 and Wang are considered to be analogous art because they are from the same field of endeavor with respect to a display device, and involve the same problem of forming the display device with suitable circuitry for repairing a disconnection in a signal line. Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the system of U.S. Patent No. 12,272,300 based on Wang wherein the pixel circuit includes: a first transistor including first, second, and third electrodes connected to first, second, and third nodes, respectively; a second transistor configured to transfer the at least one data signal to the first node; a third transistor electrically connected to the second node and the third node; a fourth transistor connected to at least one electrode of the third transistor and configured to allow a first initialization signal; and a seventh transistor configured to allow the first initialization signal or a second initialization signal different from the first initialization signal to the anode electrode. One reason for the modification as taught by Wang is to improve the hysteresis phenomenon of the drive transistor and reduce high and low frequency flicker of the pixel circuit (paragraphs[0587]-[0588] of Wang). In addition, in regard to U.S. Patent No. 12,272,300, it would have been obvious to one of ordinary skill in the art to remove the further limitations “operating in the first mode; a plurality of; for a preset time” at least since omitting the further limitations does not prevent the apparatus from functioning properly, and the claim is in “comprising” format indicating other elements could be added. In addition, dependent claims 11-19 are rejected at least based on same above reasoning and given that their limitations are similar to corresponding claims 2-9 of U.S. Patent No. 12,272,300.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,272,300. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the independent claims, mentioned above, are substantially the same.
The following is an example for comparing claim 20 of this application and respective claim 17 of U.S. Patent No. 12,272,300:
Instant Application
U.S. Patent No.
12,272,300
Claim 20
Claim 17
A method of driving a display device including a display panel, the method comprising: computing gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image or a second image based on a value resulting from the computing, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency.
A method of driving a display device including a display panel, the method comprising: computing gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image representing a low gray level or a second image representing a high gray level based on a value resulting from the computing, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency.
Independent claim 20 of the instant application teaches “A method of driving a display device including a display panel, the method comprising: computing gray level values on a frame basis for an image including a plurality of frames; and determining whether the image corresponds to a first image or a second image based on a value resulting from the computing, wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency.” However, it would have been obvious to one of ordinary skill in the art to remove the further limitations “representing a low gray level; representing a high gray level” at least since omitting the further limitations does not prevent the method from functioning properly, and the claim is in “comprising” format indicating other elements could be added.
Potentially Allowable Subject Matter
Claims 1 and 20 would be allowable if rewritten to overcome applicable double patenting rejection(s) indicated above, because for claims 1 and 20 the prior art references of record do not teach the combination of all element limitations as presently claimed. For example, in regard to claim 1 the prior art of record does not expressly teach combined concept of wherein in the first mode, the second image includes reset frames for periodically resetting a voltage of the anode electrode between refresh frames for supplying at least one data signal to at least one of the plurality of pixels. Still for example, in regard to claim 20 the prior art of record does not expressly teach combined concept of wherein the first image is displayed on the display panel based on a first driving frequency, and the second image is displayed on the display panel based on a second driving frequency higher than the first driving frequency for a preset time and thereafter is displayed based on the first driving frequency. In addition, claims 2-19 are each objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome applicable double patenting rejection(s) indicated, if any, above because for each of claims 2-19, at least in light of their dependency on independent claim 1, the prior art references of record do not teach the combination of all element limitations as presently claimed.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure and include the following:
Kwon et al., U.S. Patent Application Publication 2021/0035505 A1 (hereinafter Kwon) teaches an OLED display device performing low frequency driving.
Kim et al., U.S. Patent Application Publication 2016/0104408 A1 (hereinafter Kim I) teaches a method of reducing or preventing flicker on a display panel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDUL-SAMAD A ADEDIRAN whose telephone number is (571)272-3128. The examiner can normally be reached on Monday through Thursday, 8:00 am to 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABDUL-SAMAD A ADEDIRAN/Primary Examiner, Art Unit 2621