CTNF 19/068,941 CTNF 74911 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 2-21 are now pending in the application under prosecution and have been examined. Claim 1 has been canceled by applicant’s preliminary amendment. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented. The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art. In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent 12,242,396. Although the claims at issue are not identical, they are not patentably distinct from each other because: claims 1-20 of U.S. Patent 12,242,396 anticipate claims 2-21 of the instant application. As an example: Claim 1 (12,242,396) Claim 2 (Appl. 19/068,941) An apparatus, comprising: a processor that includes: a permission table circuit configured to store a plurality of permissions for accesses to memory, wherein the permission table circuit is indexed by a particular permission table index corresponding to a particular instruction to provide a particular permission for a particular memory access by the particular instruction ; a secondary execution privileges table circuit configured to store a plurality of secondary execution privilege values, wherein the secondary execution privileges table circuit is indexed by a particular secondary execution privileges index corresponding to the particular instruction to provide a particular secondary execution privileges value for the particular instruction ; and a control circuit coupled to the permission table circuit and the secondary execution privileges table circuit configured to: generate the particular permission table index and the particular secondary execution privileges index based on: a first value corresponding to a first memory address indicated by the particular instruction; and a second value corresponding to a second memory address indicative of a program counter value used to fetch the particular instruction; and determine, based on permissions retrieved from the permission table circuit and the secondary execution privileges table circuit, access permissions for the particular memory access by the particular instruction. An apparatus, comprising: a memory management unit circuit (MMU) configured to: receive a memory access instruction to access a particular location in a system memory; generate a primary index value and secondary index value based on: a first value associated with the particular location indicated by the memory access instruction; and a second value corresponding to a memory address indicative of a program counter value used to fetch the memory access instruction; use the primary index value to retrieve a first set of permission values from a primary permissions table; use the secondary index value to retrieve a second set of permission values from a secondary permissions table ; and determine, based on the first and second sets of permissions, access permissions for the memory access by the memory access instruction. Claim 1 of US Patent 12,242,396 is similar in substance to claim 2 of the instant patent application. The “control circuit” recited in claim 1 of the patent is logically equivalent to the “memory management unit” of the instant application as both have the same function. Therefore, claim 1 of the patent, covering similar features recited in claim 2 of the application, anticipates claim 2 of the instant application. Claim 15 (12,242,396) Claim 9 (Appl. 19/068,941) A method, comprising: receiving, in a processor of a computer system, a particular instruction to be executed by an execution pipeline circuit of the processor, the particular instruction including a reference to a first memory address; storing, by the processor in a permission table, a plurality of permissions for accesses to memory of the computer system, wherein the permission table is indexed by a permission table index; generating, by the processor, a particular permission table index for the particular instruction based on: a first value corresponding to the first memory address; and a second value corresponding to a second memory address indicating a program counter value used for fetching the particular instruction; retrieving, by the processor from the permission table using the particular permission table index, a particular permission mask for the particular instruction ; generating, by the processor, a primary index for the particular instruction based on the first memory address; retrieving, by the processor using the primary index, a base memory permission from a permission lookup table ; and enforcing, by the processor during execution of the particular instruction, a final memory permission that is based on the particular permission mask and the base memory permission. A method, comprising: receiving, in a processor of a system on a chip (SOC) implemented on one or more integrated circuits, a memory access instruction to access a particular location of a system memory, the memory access instruction including a reference to a first memory address in the memory system to be accessed; g enerating, by the processor, a primary index value and a secondary index value based on: a first value corresponding to the first memory address; and a second value corresponding to a second memory address indicating a program counter value used for fetching the memory access instruction; retrieving, by the processor using the primary index value, primary permissions for processing the memory access instruction ; retrieving, by the processor using the secondary index value, secondary permissions for processing the memory access instruction ; and enforcing, by the processor during execution of the memory access instruction, a final permission set that is based on the primary and secondary permissions. Claim 15 of US Patent 12,242,396 is similar in substance to claim 9 of the instant patent application. Claim 15 of the patent features “instruction to use permission table to access addresses”, while claim 9 of the patent features “instruction to use permission table to access location”. The two are interchangeable, therefore are similar in scope. Therefore “control circuit” recited in claim 1 of the patent is logically equivalent to the “memory management unit” of the instant application as both have the same function. Therefore, claim 15 of the patent, covering similar features recited in claim 9 of the application, anticipates claim 9 of the instant application. Independent claim 15 of the instant application is similar in scope to independent claim 11 of US Patent 12,242,396 and, therefore, is anticipated by claim 11 of the US Patent. Dependent claims 3-8, 10-14, and 16-21 cover similar features with dependent claims 2-10 and 16-20 of US Patent 12,242,396. Therefore the features of claims 2-10 and 16-20 of US Patent 12,242,396 anticipate the features of dependent claims 3-8, 10-14, and 16-21 of the instant application. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO 2018215734 A1 (BARNES) teaching apparatus comprising a processing circuitry to execute instructions of an instruction set, the processing circuitry arranged to operate in a capability domain that has capabilities used to constrain operations performed by the processing circuitry when executing instructions; a program counter capability storage element storing a program counter capability that is used by the processing circuitry to determine a program counter value identifying a plurality N of default permissions whose state is determined from N permission flags. US 20200159667 A1 (BAK et al) teaching Second Layer Address Table (SLAT) traversed to increase the speed with which a memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced. US 9251102 B2 (TUCH et al) teaching computing system includes a guest domain access control register (DACR), and guest first and second level page tables, the page tables containing domain identifiers used to obtain domain access information and access permission information, and the domain access information and the access permission information providing an effective guest access permission. The computing system provides a shadow page table, in which domain identifiers are used to identify domain access information in a processor DACR that are mapped from domain access information in the guest DACR, and in which access permissions are mapped from effective access permission information in the guest page tables and guest DACR. US 20180329835 A1 (Van REIEL et al) teaching method to include: initializing a plurality of memory protection keys associated with a plurality of page table entries associated with an address space of a processing thread; loading, to a protection key rights register associated with the processing thread, a plurality of memory access permissions referenced by the memory protection keys. CN 105247494 A (PACKER et al) teaching system on chip (SoC) or other integrated system comprising a first processor and at least one additional processor shared page table. of the shared page table may include permission bits, these permission bits comprises a processor supporting the first permission indicator and support at least one second permission indicator in the at least one additional processor. C. Ye, Y. Xu, X. Shen, X. Liao, H. Jin and Y. Solihin, "Hardware-Based Address-Centric Acceleration of Key-Value Store," 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea (South), 2021, pp. 736-748. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138 Application/Control Number: 19/068,941 Page 2 Art Unit: 2138 Application/Control Number: 19/068,941 Page 3 Art Unit: 2138 Application/Control Number: 19/068,941 Page 4 Art Unit: 2138 Application/Control Number: 19/068,941 Page 5 Art Unit: 2138 Application/Control Number: 19/068,941 Page 6 Art Unit: 2138 Application/Control Number: 19/068,941 Page 7 Art Unit: 2138 Application/Control Number: 19/068,941 Page 8 Art Unit: 2138 Application/Control Number: 19/068,941 Page 9 Art Unit: 2138 Application/Control Number: 19/068,941 Page 10 Art Unit: 2138 Application/Control Number: 19/068,941 Page 11 Art Unit: 2138 Application/Control Number: 19/068,941 Page 12 Art Unit: 2138 Application/Control Number: 19/068,941 Page 13 Art Unit: 2138 Application/Control Number: 19/068,941 Page 14 Art Unit: 2138 Application/Control Number: 19/068,941 Page 15 Art Unit: 2138 Application/Control Number: 19/068,941 Page 16 Art Unit: 2138
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