DETAILED ACTION
1.
This is in reply to an application filed on 05/13/2025. Claims 2-21 are pending examination.
2.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3.
Drawing Objection
Figures 2B-2C are objected to, because some of the elements of these figures are not labeled. Examiner suggests labeling the elements with descriptive texts based on the specification.
4.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.-The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
1. Claims 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 18:
The claim recites “the second computing component”. However, there is insufficient antecedent basis for this limitation in the claim. The examiner suggests the Replacement of “the second computing component” with “a second computing component”.
5.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-4, and 12-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 10-11, and 12 of U.S. Patent No. 12,265,613. Although the claims at issue are not identical, they are not patentably distinct from each other because all above claims of the instant application are taught by claims of Patent No. 12,265,613.
6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-21 are rejected under 35 U.S.C. 103 as being unpatentable over Sity et al. US 2022/0164297 (hereinafter Sity). in view of Shao et al. CN 106326053 (hereinafter Shao).
Regarding claim 2 Sity teaches a processing device comprising: a first computing component on a die; and a second computing component on the die, the second computing component being a redundant component of the first computing component, wherein the second computing component is located on the die adjacent to a location on the die of the first computing component within a predetermined distance (Sity teaches two or more adjacent dies [0657-0658] and fig. 38A-38C, wherein caching elements may be formed on the same semiconductor die as processing unit [0275], wherein a dies may include a plurality of memories and processors [0640-0641] and fig. 35B). Sity does not teach a predetermined distance less than a diameter of a laser spot of a laser fault injection device to mitigate a fault injection attack from the laser fault injection device. Shao substantially teaches a synchronous control unit focusing the femtosecond laser on the different position of the chip surface to different positions of the measuring chip to fault injection, and the chip to be tested is femtosecond laser irradiation under different position, wherein a focusing spot size diameter such as 900nm to 0.1 um (pg. 5 and 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sity such that the invention further includes a predetermined distance less than a diameter of a laser spot of a laser fault injection device to mitigate a fault injection attack from the laser fault injection device. One would have been motivated to do so to improve the precision of the fault injection and the safety based on the success rate of chip testing fault injection (pg. 1, Abstract).
Regarding claim 3 Sity as modified teaches the processing device of claim 2, wherein the first computing component comprises a logic block comprising a plurality of interconnected logic gates, wherein the second computing component comprises a redundant logic block comprising at least a portion of the plurality of interconnected logic gates of the first computing component (Sity teaches a plurality of logic blocks in a chip may have specialized hardware or architectures for different tasks [0501], a memory may include a plurality of gates, wherein the gates are connected to a respective one of a plurality of word lines [0506]. A plurality of redundant logic blocks [0469], [0477-0478] and fig. 16, 18-19).
Regarding claim 4 Sity as modified teaches processing device of claim 3, wherein the redundant logic block is located on the die by interleaving at least one logic gate of the redundant logic block with at least a portion of the plurality of interconnected logic gates (Sity teaches a plurality of dies may be used for fabrication of a memory chip [0640], wherein the dies may be fabricated by semiconductor layers [0664], and implementing a plurality of redundant logic blocks [0469], [0477-0478] and fig. 16, 18-20).
Regarding claim 5 Sity as modified teaches the processing device of claim 3, wherein a portion of the plurality of interconnected logic gates of the first computing component is located within the predetermined distance of at least a portion of the redundant logic block of the second computing component (Sity teaches redundant logic block set [0436] and fig. 14, and wherein a plurality of logic gates may control the direction of the signals between sub-bank controllers [0403-0404], fig. 9 and 18).
Regarding claim 6 Sity as modified teaches the processing device of claim 3, wherein the redundant logic block comprises a plurality of interconnected logic gates interconnected the same as the plurality of interconnected logic gates of the logic block of the first computing component (Sity teaches a plurality of logic blocks such as redundant business logic in a memory chip may communicate with each other via a bus [0447-0449] and fig. 16-18).
Regarding claim 7 Sity as modified teaches the processing device of claim 3, wherein the plurality of interconnected logic gates of the logic block and the redundant logic block comprise a transistor device (Sity teaches redundant logic block set [0436], fig. 14, wherein a plurality of components may include a plurality of transistors [0715], [1160] and fig. 85A).
Regarding claim 8 Sity as modified teaches the processing device of claim 2 further comprising a processing device executing instructions to cause the processing device to: process an input string of bits through the first computing component and the second computing component and compare a first output from the first computing component to a second output from the second computing component, the first output and the second output based on the processing of the input string of bits (Sity teaches a plurality of components may communicate data via a plurality of input-output bus [0642-0643], and further Shao teaches at last collected operation result with the preset correct operation result of the chip to be tested and comparing and analyzing to determine the chip to be tested is femtosecond laser irradiation position whether effective fault occurs, wherein it can judge the safety degree of the chip to be tested according to the effective error position number, and wherein the femtosecond laser photon absorption occurs in the chip to be tested, to realize an extremely small range of error injection attack (pg. 4)).
Regarding claim 9 Sity as modified teaches the processing device of claim 8, wherein the processing device executing the instructions further cause the processing device to: execute, based on a determination that the first output and the second output are different, a mitigation procedure by the processing device (Sity when detecting attack on data or commands in one or more locked memory locations, wherein a response module of controller may halt of one or more operations, such as a memory access operation associated with the detected attack. A response to a detected attack may include halting one or more operations associated with execution of a program or model, returning of a warning of an attempted attack, asserting an indication to the host or deleting the entire memory [1018]).
Regarding claim 10 Sity as modified teaches the processing device of claim 9, wherein the determination that the first output and the second output are different indicates a fault injection attack on the processing device (Shao teaches at last collected operation result with the preset correct operation result of the chip to be tested and comparing and analyzing to determine the chip to be tested is femtosecond laser irradiation position whether effective fault occurs, wherein it can judge the safety degree of the chip to be tested according to the effective error position number, and wherein the femtosecond laser photon absorption occurs in the chip to be tested, to realize an extremely small range of error injection attack (pg. 4)).
Regarding claim 11 Sity as modified teaches the processing device of claim 9, wherein the mitigation procedure comprises executing a procedure to shutdown one or more operations of the processing device based on the determination (Sity: [1018]).
In response to Claim 12: Rejected for the same reason as claim 9
In response to Claim 13: Rejected for the same reason as claim 3
In response to Claim 14: Rejected for the same reason as claim 4
In response to Claim 15: Rejected for the same reason as claim 5
In response to Claim 16: Rejected for the same reason as claim 6
In response to Claim 17: Rejected for the same reason as claim 7
In response to Claim 18: Rejected for the same reason as claim 8
In response to Claim 19: Rejected for the same reason as claim 9
In response to Claim 20: Rejected for the same reason as claim 10
In response to Claim 21: Rejected for the same reason as claim 11
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYOUB ALATA whose telephone number is (313)446-6541. The examiner can normally be reached on Monday - Friday 7:30 - 5:00 Est.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jung (Jay) Kim can be reached on (571)272-3804. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300.
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/AYOUB ALATA/Primary Examiner, Art Unit 2494
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