DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “the conductive layer” in the sixth line. The previously established “at least one conductive layer” is inclusive of more than one conductive layer. Therefore it is unclear which conductive layer corresponds to “the conductive layer”. Claims 6 and 7 are also rejected based on their dependence from claim 5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0308438 to De Ceuster.
Regarding claims 1-4, 8, and 14, De Ceuster teaches a back contact solar cell (schematically shown in Fig. 14, ¶0061-0067) comprising
A substrate 103 (Fig. 17, ¶0031), including a plurality of first doped regions (coincident with elements 101) spaced apart along a first direction (Figs. 14-19 only illustrate one first doped region, however the text is clear that the pattern repeats in a left-right direction; ¶0040), a plurality of second doped regions (coincident with 102) arranged along the first direction, and gap regions 800, wherein at least a portion of each of the plurality of second doped regions is between respective adjacent first doped regions of the plurality of first doped regions (¶0031 teaches “There are several P-type and N-type doped regions in any given solar cell…”; the layout of elements 723 in Fig. 14 show that first and second doped regions repeat and alternate along the first direction; the references to “interdigitated” metal fingers in ¶0051, 0062; also see ¶0055), and a respective gap region of the gap regions is between each first doped region and an adjacent second doped region
First doped semiconductor layers 101, respectively formed on the plurality of first doped regions, wherein each of the plurality of first doped semiconductor layers includes a first doping element (¶0032)
Second doped semiconductor layers 102, respectively formed on the plurality of second doped regions, wherein each of the plurality of second doped semiconductor layers includes a second doping element, and a conductive type of the second doping element is different from a conductive type of the first doping element
At least one conductive layer (portion of 102 intruding into gap 800 illustrated in Fig. 18), wherein each respective conductive layer of the at least one conductive layer is formed on part of a corresponding gap region, wherein a first side of the respective conductive layer is in electrical contact with a respective first doped semiconductor layer 101, and an opposing second side of the respective conductive layer is in electrical contact with a respective second doped semiconductor layer 102 adjacent to the respective first doped semiconductor layer (the portion of 102 that intrudes into gap 800 is physically and electrically continuous with the non-intruding portion of layer 102)
A passivation layer 107 (¶0030, 0036), formed over the first semiconductor layers 101, the second doped semiconductor layers 102, the at least one conductive layer and the gap regions 800 (Figs. 17, 19)
First electrodes 108 in electrical contact with the first doped semiconductor layers 101
Second electrodes 109 in electrical contact with the second doped semiconductor layers 102.
Per claim 2, De Ceuster teaches the limitations of claim 1. A ratio of a contact length where the respective conductive layer is in contact with the respective first doped semiconductor layer 101 to an extended length of the corresponding gap region is less than or equal to 0.1% to 10% (¶0068).
The claim recites a sentence structure “wherein in response to the first doped regions and the second doped regions being alternately arranged along the first direction…”. Based on context, this limitation is treated as optional or conditional, so that it does not carry patentable weight unless the regions are arranged as claimed. This is also the interpretation of “in response to the second doped region surrounding the respective first doped region…”.
De Ceuster teaches that the first doped regions 101 and the second doped regions are alternately arranged along the first direction (Ibid.). The length of the corresponding gap regions along a second direction (up-down direction of Figs. 14, 16, 18) is that of the cell (¶0068). The phrase “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region” is interpreted in light of the instant disclosure, specifically instant Figure 12 and paragraphs [0117]-[0122]. The phrase is interpreted to mean that a conductive layer is not formed at an end of a gap region. As the gap regions extend the entire length of the cell, and the locations of the second conductive layers 723 in Fig. 14 are not shown at the end of the cell, De Ceuster is interpreted to anticipate “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region”.
Per claims 3 and 4, De Ceuster teaches the limitations of claim 2. The limitation that “wherein in response to the inner circumference of the corresponding gap region being the extended length of the corresponding gap region” means that the limitations that follow only carry patentable weight when the regions are arranged so that the respective doped regions surrounds the respective first doped region. De Ceuster does not teach this configuration of elements; therefore the limitations of claims 3 and 4 do not carry patentable weight, and De Ceuster still anticipates.
Per claim 8, De Ceuster teaches the limitations of claim 1. The respective conductive layer is located on the substrate 103 corresponding to the corresponding gap region, and is in electrical contact with a side surface of the first doped semiconductor layer 101 (Fig. 19).
Per claim 14, De Ceuster teaches the limitations of claim 1. A material of the respective conductive layer is substantially the same material as the respective second doped semiconductor layer 102 (Ibid.).
Claim(s) 1-4, 8-12, 14, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2024/0313136 to Wang.
Regarding claims 1-4, 8-12, 14, and 16, Wang teaches a back contact solar cell comprising
A substrate 10 (Fig. 6, ¶0041, 0042, 0055), including a plurality of first doped regions 122 spaced apart along a first direction (left-right in Fig. 3), a plurality of second doped regions 121 arranged along the first direction, and gap regions (Fig. 6 illustrates a region 123 of Fig. 3, but ¶0061 clarifies that nothing is provided on the side of the groove 122 in all areas except for 123, so that the two regions are physically separated at least by the side of the groove), wherein at least a portion of each of the second doped regions is between respective adjacent first doped regions of the plurality of first doped regions, and a respective gap region of the gap regions is between each first doped region and an adjacent second doped region (¶0043)
First doped semiconductor layers 20, respectively formed on the plurality of first doped regions 122, wherein each of the plurality of first doped semiconductor layers include a first doping element (¶0045)
Second doped semiconductor layers 30, respectively formed on the plurality of second doped regions 121, wherein each of the plurality of second doped semiconductor layers 30 includes a second doping element, and a conductive type of the second doping element is different from a conductive type of the first doping element
At least one conductive layer 31 (¶0046, 0047), wherein each respective conductive layer of the at least one conductive layer is formed on part of a corresponding gap region (31 is formed on a side of the groove), wherein a first side of the respective conductive layer is in electrical contact with a respective first doped semiconductor layer 20 adjacent to the respective first doped semiconductor layer (¶0049-0053), and an opposing second side of the respective conductive layer is in electrical contact with a respective second doped semiconductor layer 30 adjacent to the respective first doped semiconductor layer (portions 31 extend down the side of groove to meet the bulk of layer 30)
A passivation layer 60, formed over the first doped semiconductor layers 20, the second doped semiconductor layers 30, the at least one conductive layer 31 and the gap regions (¶0060)
First electrodes 40 in electrical contact with the first doped semiconductor layers 20 (¶0059)
Second electrodes 50 in electrical contact with the second doped semiconductor layers 30.
Per claim 2, Wang teaches the limitations of claim 1. In an embodiment, a ratio of a contact length where the respective conductive layer is in contact with the respective first doped semiconductor layer to an extended length of the corresponding gap region is 5% (¶0105, 0106).
The claim recites a sentence structure “wherein in response to the first doped regions and the second doped regions being alternately arranged along the first direction…”. Based on context, this limitation is treated as optional or conditional, so that it does not carry patentable weight unless the regions are arranged as claimed. This is also the interpretation of “in response to the second doped region surrounding the respective first doped region…”.
Wang teaches that the first doped regions 20 and the second doped regions 30 are alternately arranged along the first direction (left-right in Fig. 3). The length of the corresponding gap regions (“side wall surface” of ¶0045) along a second direction (up-down direction) is that of the cell, or 10 cm in a particular embodiment (¶0106). The phrase “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region” is interpreted in light of the instant disclosure, specifically instant Figure 12 and paragraphs [0117]-[0122]. The phrase is interpreted to mean that a conductive layer is not formed at an end of a gap region. As the gap regions extend the entire length of the cell, and the locations of the second conductive layers 123 in Fig. 3 are not shown at the end of the cell, Wang is interpreted to anticipate “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region”.
Per claims 3 and 4, Wang teaches the limitations of claim 2. The limitation that “wherein in response to the inner circumference of the corresponding gap region being the extended length of the corresponding gap region” means that the limitations that follow only carry patentable weight when the regions are arranged so that the respective doped regions surrounds the respective first doped region. Wang does not teach this configuration of elements; therefore the limitations of claims 3 and 4 do not carry patentable weight, and Wang still anticipates.
Per claim 8, Wang teaches the limitations of claim 1. In an embodiment, the respective conductive layer 31 is located on the substrate 10 corresponding to the corresponding gap region, and is in electrical contact with a side surface of the respective first doped semiconductor layer 20 (layer 31 wraps around the edge of layer 20 in Fig. 9, ¶0078).
Per claim 9, Wang teaches the limitations of claim 1. In an embodiment, the respective first doped semiconductor layer 20 includes an extension portion 21 located on part of the corresponding gap region (Fig. 9 shows 21 extending over the sidewall of the groove 121), and the respective conductive layer 31 is in electrical contact with both a top surface 212 and a side surface 213 of the extension portion (¶0078).
Per claim 10, Wang teaches the limitations of claim 8. The respective conductive layer 31 further extends to part of a top surface 212 of the respective first doped semiconductor layer 20 in the respective first doped region 122, and the respective conductive layer is physically insulated from the first electrodes 40 (Fig. 9).
Per claim 11, Wang teaches the limitations of claim 10. A top surface of the respective second doped semiconductor layer 30 is lower than a top surface of the respective first doped semiconductor layer 20 (the majority of layer 30 is in groove 121, the majority of layer 20 is on non-groove 122).
Per claim 12, Wang teaches the limitations of claim 11. The respective conductive layer 31 includes a first conductive layer and a second conductive layer (see Marked-up Fig. 9 below), the first conductive layer is located on a side surface of the respective first doped semiconductor layer 20, the second conductive layer is located on a top surface of the respective first doped semiconductor layer, and an acute angle is formed between a bottom surface of the first conductive layer and a bottom surface of the second conductive layer.
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Per claim 14, Wang teaches the limitations of claim 1. The material of the respective conductive layer is 31 is substantially the same as a material of the respective second doped semiconductor layer 30 (conductive layer is an extension of layer 30).
Per claim 16, Wang teaches the limitations of claim 9. The respective conductive layer 31 further extends to part of a top surface 212 of the respective first doped semiconductor layer 20 in the respective first doped region 122, and the respective conductive layer is physically insulated from the first electrodes 40 (Fig. 9).
Regarding claims 17-20, Wang teaches a photovoltaic module comprising
At least one solar cell string, each formed by connecting a plurality of back-contact solar cells 100 (Figs. 1, 2, ¶0039, 0040)
A connecting member (“welding strips”, configured to electrically connect two adjacent back-contact solar cells 100 of the plurality of back-contact solar cells
An encapsulation film (“front adhesive film” and/or “rear adhesive film”), configured to cover a surface of the at least one solar cell string
A cover plate (“front plate”), configured to cover a surface of the encapsulation film that is away from the at least one solar cell string
Wherein each of the plurality of back-contact solar cells 100 includes
A substrate 10 (Fig. 6, ¶0041, 0042, 0055), including a plurality of first doped regions 122 spaced apart along a first direction (left-right in Fig. 3), a plurality of second doped regions 122 arranged along the first direction, and gap regions (Fig. 6 illustrates a region 123 of Fig. 3, but ¶0061 clarifies that nothing is provided on the side of the groove 122 in all areas except for 123, so that the two regions are physically separated at least by the side of the groove), wherein at least a portion of each of the second doped regions is between respective adjacent first doped regions of the plurality of first doped regions, and a respective gap region of the gap regions is between each first doped region and an adjacent doped region (¶0043)
First doped semiconductor layers 20, respectively formed on the plurality of first doped regions 122, wherein each of the plurality of first doped semiconductor layers include a first doping element (¶0045)
Second doped semiconductor layers 30, respectively formed on the plurality of second doped regions 121, wherein each of the plurality of second doped semiconductor layers 30 includes a second doping element, and a conductive type of the second doping element is different from a conductive type of the first doping element
At least one conductive layer 31 (¶0046, 0047), wherein each respective conductive layer of the at least one conductive layer is formed on part of a corresponding gap region (31 is formed on a side of the groove), wherein a first side of the respective conductive layer is in electrical contact with a respective first doped semiconductor layer 20 adjacent to the respective first doped semiconductor layer (¶0049-0053)
A passivation layer 60, formed over the first doped semiconductor layers 20, the second doped semiconductor layers 30, the at least one conductive layer 31 and the gap regions (¶0060)
First electrodes 40 in electrical contact with the first doped semiconductor layers 20 (¶0059)
Second electrodes 50 in electrical contact with the second doped semiconductor layers 30.
Per claim 18, Wang teaches the limitations of claim 17. In an embodiment, a ratio of a contact length where the respective conductive layer is in contact with the respective first doped semiconductor layer to an extended length of the corresponding gap region is 5% (¶0105, 0106).
The claim recites a sentence structure “wherein in response to the first doped regions and the second doped regions being alternately arranged along the first direction…”. Based on context, this limitation is treated as optional or conditional, so that it does not carry patentable weight unless the regions are arranged as claimed. This is also the interpretation of “in response to the second doped region surrounding the respective first doped region…”.
Wang teaches that the first doped regions 20 and the second doped regions 30 are alternately arranged along the first direction (left-right in Fig. 3). The length of the corresponding gap regions (“side wall surface” of ¶0045) along a second direction (up-down direction) is that of the cell, or 10 cm in a particular embodiment (¶0106). The phrase “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region” is interpreted in light of the instant disclosure, specifically instant Figure 12 and paragraphs [0117]-[0122]. The phrase is interpreted to mean that a conductive layer is not formed at an end of a gap region. As the gap regions extend the entire length of the cell, and the locations of the second conductive layers 123 in Fig. 3 are not shown at the end of the cell, Wang is interpreted to anticipate “a length of the corresponding gap region along a second direction is the extended length of the corresponding gap region”.
Per claims 19 and 20, Wang teaches the limitations of claim 18. The limitation that “wherein in response to the inner circumference of the corresponding gap region being the extended length of the corresponding gap region” means that the limitations that follow only carry patentable weight when the regions are arranged so that the respective doped regions surrounds the respective first doped region. Wang does not teach this configuration of elements; therefore the limitations of claims 19 and 20 do not carry patentable weight, and Wang still anticipates.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5-7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over De Ceuster as applied to claim 1 above.
Regarding claims 5-7 and 15, De Ceuster teaches the limitations of claim 1. De Ceuster teaches that each of the plurality of first semiconductor regions 101 is defined by a corresponding adjacent gap region (Fig. 8A shows that the first and second semiconductor regions are not fully defined until a gap region is formed, ¶0045). Further, although this is not explicitly illustrated, each of the gap regions extends the entire dimension of the cell in the second direction (¶0068). Therefore a skilled artisan would understand that each gap region has one distinct first semiconductor region portion to its left (in the frame of Figs. 15, 16, 18) and one distinct second semiconductor region to its right. Fig. 14 illustrates columns of either four elements 723, coincident with conductive layers, separated in the second direction, or of two elements 723, separated in the second direction. These columns alternate in the first direction. Therefore Fig. 14 illustrates at least nine gap regions, with corresponding adjacent first doped semiconductor layers and second semiconductor layers (see Marked-up Fig. 14 below).
A skilled artisan would understand that the embodiment of Fig. 14 is schematic, and that not all locations of conductive layers are illustrated (¶0061). Further, a skilled artisan would not understand the Fig. to mean that an actualized solar cell has only 9 gap portions separated along the first direction. De Ceuster does not seem to specifically recite a number of gap portions, first doped semiconductor layers, or second semiconductor layers present in an actual solar cell.
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Regardless, if it is (arbitrarily) presumed that a solar cell is laid out as shown in Fig. 14, the first doped semiconductor layers include a plurality of first portions, wherein the plurality of first portions (formed to the left of each of the gap regions) are ones of the first doped semiconductor layers that are in electrical contact with the at least one conductive layer (indeed each first doped semiconductor layer is in electrical contact with more than one of the at least one conductive layer). Under this presumption, the first doped semiconductor layers include only a plurality of first portions.
In a likely more realistic situation, in which not every gap region has an associated column of locations 723 coincident with a conductive layer, some of the first doped semiconductor layers are a plurality of second portions, wherein the plurality of second portions are ones of the first doped semiconductor layers that are not in direct contact with the conductive layer. In fact, Fig. 24 illustrates an extreme situation, in which only one conductive layer (also coincident with 723) is present on the whole cell (¶0071-0074). Therefore, this schematic cell comprises only one first doped semiconductor layer that is a first portion, with every other first doped semiconductor layer comprising the plurality of second portions.
De Ceuster explicitly teaches that it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to vary the number of first portions, number of second portions, and the spatial distribution of such portions across the solar cell with respect to gap portions, in order to avoid cell heating (¶0066-0076). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective variable, without producing any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
Therefore De Ceuster renders obvious the claimed proportion N1/N, and the claimed range of N2.
Claim(s) 5-7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above.
Regarding claims 5-7 and 15, Wang teaches the limitations of claim 1. Wang teaches that each of the plurality of first semiconductor regions 20 is defined by a corresponding adjacent gap region (“side wall surface” of ¶0045). Fig. 3 illustrates that two first doped semiconductor layers 20 (furthest to the left and furthest to the right) are in electrical contact with a corresponding conductive layer (at location 123). Therefore the embodiment of Fig. 3 illustrates a plurality of first portions, wherein the plurality of first portions are ones of the first doped semiconductor layers that are in electrical contact with the at least one conductive layer. Further, the remaining two ones of the first doped semiconductor layers 20 are not in direct contact with a conductive layer, and therefore a plurality of second portions is present.
A skilled artisan would understand that Fig. 3 is schematic. However, Wang does teach that it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to vary the location, length, and number of locations where a respective conductive layer is in contact with a respective first doped semiconductor layer in order to achieve the desired repair effect (¶0049-0054, 0098-0110).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective variable, without producing any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
Therefore Wang renders obvious the claimed proportion N1/N, and the claimed range of N2.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 12 above.
Regarding claim 13, Wang teaches the limitations of claim 12. Wang does not specifically provide an orthographic projection of the first conductive layer on a projection plane and an orthographic projection of the second conductive layer on the projection plane. Such a projection would be similar to the view of Fig. 3. The edges of the first and second conductive layer may touch (as illustrated by the dashed line of modified-Fig. 9 above, which approximately coincides with the edges of those layers), but it is not clear that the projections would overlap. However, only small changes in shape of the first doped semiconductor layer and/or the second doped semiconductor layer would result in overlap (for instance, if the side surface of 20 were flattened at the top, the top surface of the first surface of 20 would extend further to the right). Therefore it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to form orthographic projections of the first conductive layer and second conductive layer to overlap, since it would merely require a change of form or shape. The change in form or shape, without any new or unexpected results, is an obvious engineering design. See In re Dailey, 149 USPQ 47 (CCPA 1976) (see MPEP § 2144.04).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2025/0374707.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan S Cannon whose telephone number is (571)270-7186. The examiner can normally be reached M-F, 8:30am-5:30pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Barton can be reached at (571) 272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Ryan S. Cannon
Primary Examiner
Art Unit 1726
/RYAN S CANNON/ Primary Examiner, Art Unit 1726