DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 3-4-2025 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (USPAP 2020/0403634) in view of DU (USPAP 2017/0288698).
Claims 1 and 11:
Zhang substantially teaches the claimed invention. Zhang teaches a method and an apparatus for techniques to improve performance related to at least data reads from a memory, the method comprising: retrieving stored data from a storage system and detecting noise or errors that may be included in the retrieved data (see par. 0036). Zhang teaches that a detector (130) performs either soft detection or hard detection on the retrieved stored data thereby outputting a decision and/or reliability information (see par. 0036). Zhang teaches that a hard decision output a decision bit that is either a (“1” or “0”) and a soft decision outputs a log-likelihood ratio (LLR) wherein the sign indicates the decision i.e., a positive sign value corresponds to a “1” decision and a negative sign value correspond to a “0” decision (see par. 0036).
Zhang teaches that the decision output from the detector is then passed to a low density parity check decoder (140) which performs decoding on the received decision and reliability information (see par. 0037). Zhang teaches that a message passing algorithm (“symmetric bit-flip (BF) decoding”) is generally used to decode LDPC codes (see par. 0040). Zhang teaches that the decoder performs both hard decision decoding and soft decision decoding wherein a number of decoding iterations are performed depending on the syndrome of the codeword (see par. 0043).
Zhang teaches storing an information bit and/or a parity bit in a cell wherein to check whether the cell contains a “0” or a “1”, a voltage is read and compared to a voltage threshold to identify the relevant voltage level and the bit value (see par. 0051). Zhang teaches that a 0-to-1 error can occur when the voltage measurement indicates that the bit should be read as a 1 (see par. 0051).
Zhang teaches that asymmetric error ratios in NAND flash memories are measured wherein error ratio curves are generated (see par. 0054). Zhang teaches that a computer system having a specific hardware performs specific operations such as estimating the first number of errors and performing decoding on the estimates (see par. 0060). Zhang teaches that after the first number of errors E01 and the second number of errors E10 are estimated, the computer system performs the decoding of the codewords based on the decoding procedure of either soft or hard decision (see par. 0061).
Zhang teaches that the computer system determines a flip bit count E as a function of the checksum and estimates the first number of errors based on the first flip bit count (see par. 0068). Zhang teaches that the computer system can determine a ratio of the errors (see par. 0070). Zhang further teaches that prior to decoding, estimating the asymmetric ratio for probabilities of 0-to-1 and 1-to 0 and using the estimated ratio as an input into the decoder (see par. 0027 et seq.).
Zhang fails to specifically teach the limitation of “comparing the asymmetric ratio to an asymmetric ratio threshold in order to determine whether to continue to iterating of the symmetric BF decoding or to switch to the asymmetric BF decoding; however, Du in an analogous art teaches a method and an apparatus for saving power during a bit flipping algorithm for a certain number of iterations. I.e., Du teaches the steps for deciding when to switch to a different decoding mode based on the number of iterations that are outside the selected threshold and determining when to end a bit flipping algorithm during hard decision soft decoding for a low-density parity check (LDPC) decoding operation. Du teaches that if the value for each iteration is less than or equal to the corresponding column weight divided by 2, then it’s an indication that the decoding mode should be switched (see par. 0018).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the steps of hard decision decoding of Zhang to include the power saving decoding steps of DU of switching the decoding operation based on the assessment of the decoding iteration for a bit flipping algorithm. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method for modifying the hard decision decoding to include switching decoding operations for a bit flipping algorithm to save power as taught by DU (see par. 0009).
As per claim 3, Zhang teaches using the asymmetric ratio in the decoding procedure to improve the decoding performance (see par. 0029).
Allowable Subject Matter
Claims 2, 4 to 10, and 12 to 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sharifi et al. Implementing the Han-Kobayashi scheme using low density parity check codes over Gaussian interference, channels, IEEE.
Kaynak et al. (USPAP 2024/0168847) discloses a method and an apparatus for efficient use of memory to support soft information in bit flipping decoders.
Anholt et al. (USP 8,429,498 B1) teaches a decoding apparatus including dual ECC decoder.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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