DETAILED ACTION
This Office action is in response to the application filed on 04 March 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukuhara et al. (US 2011/0095738; hereinafter “Fukuhara”).
In re claim 1, Fukuhara discloses a semiconductor device (Figs. 1A, 2B, 14B) comprising:
a power device (Fig. 1A: M18) that supplies current to a load (Load);
a current detection circuit (6; Fig. 14B) that detects current flowing through the power device ([0016], [0046]);
a device control circuit (2, 3, 4, 5) that controls the current flowing through the power device based on a first detection current detected by the current detection circuit and an input signal ([0040], [0043]);
an overrange comparison circuit (7) that outputs an overrange signal when the voltage of the power device exceeds a predetermined voltage ([0044], [0046]), and
an abnormal signal generation circuit (Fig. 2B) that outputs an abnormal signal indicating an overcurrent state of the power device based on a second detection current detected by the current detection circuit and the overrange signal ([0046], [0047]).
In re claim 2, Fukuhara discloses wherein the power device includes a power transistor (Fig. 1A: M18 or Fig. 14B: M210) having a pair of terminals including a terminal connected to the load (source connected to Load at terminal OUT) and a gate terminal connected to the device control circuit (control circuit 3 at terminal GATE),
wherein the current detection circuit includes a sense transistor (M212) having a pair of terminals and a gate terminal connected to the gate terminal of the power transistor (terminal GATE), and generates the first detection current (at terminal Sense in Fig. 14B) and the second detection current (at terminal IS in Fig. 1B) based on the current flowing between the pair of terminals of the sense transistor ([0016]), and
wherein the overrange comparison circuit compares the voltage between the pair of terminals of the power transistor with the predetermined voltage and outputs the overrange signal when the voltage between the terminals exceeds the predetermined voltage ([0046]).
In re claim 3, Fukuhara discloses wherein the power transistor includes a first power transistor (Fig. 1A: M18 or Fig. 14B: M210) having one terminal connected to a first voltage terminal to which a first voltage is supplied (VCC), another terminal connected to a load terminal to which the load is connected (Load at terminal OUT), and a gate terminal connected to the device control circuit (control circuit 3 at terminal GATE),
wherein the sense transistor includes a first sense transistor (M212) having one terminal connected to the first voltage terminal (VCC) and a gate terminal connected to the gate terminal of the first power transistor (GATE), and
wherein the current detection circuit includes a first control circuit (M211, M213, R210, C210) that operates so that the voltage of the other terminal of the first sense transistor matches the voltage of the other terminal of the first power transistor (sources of M212, M210 coupled to terminal OUT so that they will have the same voltage), and the first control circuit generates the second detection current corresponding to the first power transistor ([0016]).
Allowable Subject Matter
Claims 4-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the closest prior art in Fukuhara discloses the invention according to claim 2 as explained above, but does not further disclose wherein the power transistor includes a second power transistor having another terminal connected to a second voltage terminal to which a second voltage is supplied, one terminal connected to a load terminal to which the load is connected, and a gate terminal connected to the device control circuit, wherein the sense transistor includes a second sense transistor having another terminal connected to the second voltage terminal and a gate terminal connected to the gate terminal of the second power transistor, and wherein the current detection circuit includes a bidirectional circuit connected between one terminal of the second power transistor and one terminal of the second sense transistor, which operates to match the terminal voltage b tween the pair of terminals of the second sense transistor with the terminal voltage between the pair of terminals of the second power transistor, and a second control circuit that operates so that the voltage of one terminal of the second sense transistor matches the voltage of one terminal of the second power transistor, and the second control circuit generates the second detection current corresponding to the second power transistor.
Moreover, the additional prior art on record does not provide an obvious suggestion to modify Fukuhara so as to arrive at the claimed features.
With respect to claim 5, the closest prior art in Fukuhara discloses the invention according to claim 2 as explained above, but does not further disclose wherein the abnormal signal generation circuit includes an overrange current source that outputs an overrange current corresponding to the overrange signal, an adder circuit that adds the second detection current and the overrange current, and an overcurrent comparison circuit that compares the output of the adder circuit with a predetermined current and outputs the abnormal signal.
Moreover, the additional prior art on record does not provide an obvious suggestion to modify Fukuhara so as to arrive at the claimed features.
With respect to claim 6, the closest prior art in Fukuhara discloses the invention according to claim 2 as explained above, but does not further disclose wherein the abnormal signal generation circuit includes an overcurrent comparison circuit that outputs an overcurrent signal when the second detection current exceeds a predetermined current, and a logic circuit that performs a logical OR between the overcurrent signal and the overrange signal and outputs it as the abnormal signal.
Moreover, the additional prior art on record does not provide an obvious suggestion to modify Fukuhara so as to arrive at the claimed features.
With respect to claim 7, the closest prior art in Fukuhara discloses the invention according to claim 2 as explained above, but does not further disclose a switch that turns on during diagnosis according to a diagnostic signal, anda current source connected to the overrange comparison circuit via the switch to supply current.
Moreover, the additional prior art on record does not provide an obvious suggestion to modify Fukuhara so as to arrive at the claimed features.
Claim 8 contains limitations that are substantially similar to those of claim 4, and therefore claim 8 would be allowable for the same reasons as explained above.
Claims 9-10 both depend, either directly or indirectly, from claim 8 and so would be allowable for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2009/0039869 discloses a Cascode Current Sensor For Discrete Power Semiconductor Devices including overcurrent sensing and protection using a replica device.
US 2024/0201231 discloses Current Sense Circuitry including overcurrent sensing and protection using replica devices.
US 2025/0080100 discloses safe operating area (SOA) protection of a power transistor including combined overcurrent and overvoltage sensing and protection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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