Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on March 04, 2025 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The title is meant to have an “informative value in indexing, classifying, searching”. See MPEP606.01.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-13 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Iizawa et. al. U.S Patent No. 2023/0281129 (hereinafter Iizawa).
Regarding Claim 11 Iizawa teaches a data processing method comprising: selectively performing one of: receiving prefetched data from a central processing unit (CPU) and storing the prefetched data in a memory of a graphics processing unit (GPU), and transmitting delayed offload data of the memory of the GPU to the CPU(Fig.1, 2, 6,10-12; Para33-36 "transfer (writing) of a feature map from the GPU memory 40 to the CPU memory 20 is also referred to as offload. Transfer (reading) of a feature map from the CPU memory 20 to the GPU memory 40 is also referred to as prefetch" Para91-95 "In step S74, the scheduler 12 executes prefetch in response to the prefetch request with priority over offload" ); and
performing an operation of the GPU in parallel with the receiving and storing of the prefetched data or the transmitting of the delayed offload data, wherein the prefetched data comprises input data of the operation to be performed by the GPU, and the delayed offload data comprises output data that has not been offloaded after completion of operation on the GPU (Fig.1,2; 12;Para34-36, 40 "For example, the device allocator 14 sets, as a bandwidth to be allocated to each workload WL, B/111 obtained by dividing the bandwidth B by the number m of workloads WL executed in parallel" Para91-95).
Regarding claim 12, Iizawa teaches all the limitations of the base claims as outlined above.
Further, Iizawa teaches wherein the GPU comprises an operation stream and a data copy stream, wherein the GPU performs the receiving of the prefetched data and the transmitting of the delayed offload data through the data copy stream and performs the operation of the GPU by receiving an operation task assigned by the CPU through the operation stream(Fig.5;6; Para6,10-12; Para20-21,33-36,64-65;Para91-95).
Regarding claim 13, Iizawa teaches all the limitations of the base claims as outlined above.
Further, Iizawa teaches wherein the operation of the GPU comprises an operation related to a model, the prefetched data comprises input data of a layer for the operation related to the model, and the delayed offload data comprises output data that has not been offloaded after completion of an operation of a layer of the model (Fig.5;6; Para6,10-12; Para20-21 "In training of a deep neural network using backpropagation, a workload that executes the training updates a weight to be used in each layer by executing backward propagation processing using learning data of each layer calculated in forward propagation processing" Para33-36,64-65;Para91-95).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2,8-10,14-16, are rejected under 35 U.S.C. 103 as being unpatentable over Iizawa et. al. U.S Patent No. 2023/0281129 (hereinafter Iizawa) in view of He et. al. US Patent Pub. No. 2021/0208951 (hereinafter He).
Regarding Claim 1, Iizawa teaches a data processing method comprising: determining an memory size of a graphics processing unit (GPU) (Fig.4,12; Para34-36, 40; Para91-95 "In step S72 in FIG. 12, the scheduler 12 determines whether the free space of the GPU memory 40 corresponding to the workload WL requesting the offload or prefetch is equal to or larger than a first threshold in the free space management table 24 in FIG. 4."); and based on the memory size of the GPU, selectively performing one of: transmitting prefetched data of a memory of a central processing unit (CPU) to the GPU (Fig.1, 2, 6,10-12; Para33-36 "transfer (writing) of a feature map from the GPU memory 40 to the CPU memory 20 is also referred to as offload. Transfer (reading) of a feature map from the CPU memory 20 to the GPU memory 40 is also referred to as prefetch" Para91-95 "In step S74, the scheduler 12 executes prefetch in response to the prefetch request with priority over offload" ); and receiving delayed offload data from the GPU and storing the delayed offload data in the memory of the CPU, wherein the prefetched data comprises input data for an operation to be performed by the GPU, the delayed offload data comprises output data that has not been offloaded after completion of the operation on the GPU, and the transmitting of the prefetched data or the receiving of the delayed offload data is executed in parallel with the operation of the GPU (Fig.1,2,4, 12;Para34-36, 40 "For example, the device allocator 14 sets, as a bandwidth to be allocated to each workload WL, B/111 obtained by dividing the bandwidth B by the number m of workloads WL executed in parallel" Para91-95 "In step S72 in FIG. 12, the scheduler 12 determines whether the free space of the GPU memory 40 corresponding to the workload WL requesting the offload or prefetch is equal to or larger than a first threshold in the free space management table 24 in FIG. 4.").
However, Iizawa fails to teach but He teaches determining an idle memory size of a graphics processing unit (GPU) (Fig.3; Para47-48 "the GPU resource pool records information of all virtual GPUs in an idle status"Para73).
Iizawa and He are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Iizawa, and incorporating the idle memory size, as taught by He.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by He (Para3-7).
Regarding claim 2, the combination of Iizawa and He teaches all the limitations of the base claims as outlined above.
Further, Iizawa teaches wherein the operation of the GPU comprises an operation related to a model, the prefetched data comprises input data of a layer for the operation related to the model, and the delayed offload data comprises output data that has not been offloaded after completion of an operation of a layer of the model (Fig.5;6; Para6,10-12; Para20-21 "In training of a deep neural network using backpropagation, a workload that executes the training updates a weight to be used in each layer by executing backward propagation processing using learning data of each layer calculated in forward propagation processing" Para33-36,64-65;Para91-95).
Regarding claim 8, the combination of Iizawa and He teaches all the limitations of the base claims as outlined above.
Further, Iizawa teaches wherein the determining of the idle memory size of the GPU comprises: determining a peak value of memory use of the GPU; and determining the idle memory size of the GPU based on a total memory size of the GPU and the peak value of memory use of the GPU(Fig.1,2,4, 12;Para34-36, 40 "For example, the device allocator 14 sets, as a bandwidth to be allocated to each workload WL, B/111 obtained by dividing the bandwidth B by the number m of workloads WL executed in parallel" Para91-95 "In step S72 in FIG. 12, the scheduler 12 determines whether the free space of the GPU memory 40 corresponding to the workload WL requesting the offload or prefetch is equal to or larger than a first threshold in the free space management table 24 in FIG. 4.").
Regarding claim 9, the combination of Iizawa and He teaches all the limitations of the base claims as outlined above.
Further, Iizawa teaches wherein the determining of the peak value of memory use of the GPU comprises: when the transmitting of the prefetched data and the receiving of the delayed offload data is serially performed with the operation related to the model of the GPU in an initial predetermined number of iterations of the operation related to the model, determining the peak value of memory use of the GPU during the initial predetermined number of iterations(Fig.1,2,4, 12;Para34-36, 40,Para91-95).
Regarding claims 10, 14-16, the combination of Iizawa and He teaches these claims according to the reasoning set forth in claim 1,2,8,9.
Allowable Subject Matter
Claims 3-7, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record , listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure.
NPL-Rhu et.al. teaches Virtualized Deep Neural Networks based on GPU and CPU memory.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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