DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8, 9, 11-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abedifard et al. (US 2004/0160826).
Consider claim 1, Abedifard et al. discloses a method of operating a non-volatile memory (NVM) device, in response to a fault in at least one memory subsection in an addressable memory section of the NVM device, the NVM device comprising a spare memory section including spare memory subsections configured to substitute for respective faulty memory subsections in the addressable memory section of the NVM device, and the method comprising: comparing addresses of memory subsections of the addressable memory section that is a candidate for access with a set of faulty memory subsection addresses, the set including at least one address of a faulty memory subsection having coupled therewith a mask indicative of a related fault typology; and substituting, with a spare memory subsection in the spare memory section, the memory subsections of the addressable memory section that is the candidate for access, for which the comparing the addresses indicates a match by way of identity of the compared addresses or identity of the compared addresses having applied thereto address masking with the mask indicative of the related fault typology (Fig. 1, 2, 4, 7, [0029], [0031], [0032], [0042], Abedifard et al. discloses non-volatile memory that can have defective rows and columns. Redundant rows and columns are redirected to in lieu of the defective rows and columns. Redundant circuitry is used to determine if an address is a defective address stored in register 40. An error code (mask) is appended to the defective address.).
Consider claim 2, Abedifard et al. discloses the method according to claim 1, further comprising storing faulty memory addresses of the set of faulty memory subsection addresses in respective redundancy registers of a plurality of redundancy registers (Fig. 2, [0032], Abedifard et al. discloses registers 40 includes faulty memory addresses with error codes attached.).
Consider claim 3, Abedifard et al. discloses the method according to claim 2, further comprising: coupling to the redundancy registers in the plurality of redundancy registers respective redundancy mode registers; and storing in the respective redundancy mode registers respective masks indicative of a related fault typology, a respective faulty memory address and the mask indicative of the related fault typology coupled therewith are stored in a redundancy register and in the respective redundancy mode register coupled therewith (Fig. 2, [0032], Abedifard et al. discloses registers 40 includes faulty memory addresses with error codes attached. Each error code indicates the type of error.).
Consider claim 4, Abedifard et al. discloses the method according to claim 3, wherein: a set of redundancy registers in the plurality of redundancy registers is coupled to a same respective redundancy mode register; and the faulty memory address stored in the redundancy register of the set of redundancy registers is coupled to the mask indicative of the related fault typology stored in the same respective redundancy mode register (Fig. 2, [0032], Abedifard et al. discloses registers 40 includes faulty memory addresses with error codes attached. Each error code indicates the type of error.).
Consider claim 5, Abedifard et al. discloses the method according to claim 3, wherein the respective masks indicative of the related fault typology comprise at least one first mask indicative of a first related fault typology and at least one second mask indicative of a second related fault typology, the first mask and the second mask being stored in a first redundancy mode register and in a second redundancy mode register, the first mask and the second mask being either equal or different therebetween ([0033], Abedifard et al. discloses having error codes that can signify different types of errors including row to row short sand isolated errors.).
Consider claim 6, Abedifard et al. discloses the method according to claim 2, further comprising storing the mask indicative of the related fault typology in a memory redundancy mode register, the fault typology being a fault typology of the addressable memory section ([0033], Abedifard et al. discloses having error codes, in registers 40, that can signify different types of errors including row to row short sand isolated errors.).
Consider claim 8, Abedifard et al. discloses the method according to claim 1, wherein the comparing the addresses of the memory subsections of the addressable memory section that is the candidate for access with the set of faulty memory subsection addresses comprises declaring the match by way of identity of the compared addresses in response to the addresses being compared exhibiting a bit-to-bit equality (Fig. 1, 2, 4, 7, [0029], [0031], [0032], [0042], Abedifard et al. discloses non-volatile memory that can have defective rows and columns. Redundant rows and columns are redirected to in lieu of the defective rows and columns. Redundant circuitry is used to determine if an address is a defective address stored in register 40 by seeing if they match. An error code (mask) is appended to the defective address.).
Consider claim 9, Abedifard et al. discloses the method according to claim 1, wherein the comparing the addresses of the memory subsections of the addressable memory section that is the candidate for access with the set of faulty memory subsection addresses comprises declaring the match by way of identity of the compared addresses having applied thereto address masking with the mask indicative of the related fault typology in response to the addresses being compared exhibiting bit-to-bit equality of bits left unmasked by the mask (Fig. 1, 2, 4, 7, [0029], [0031], [0032], [0042], Abedifard et al. discloses non-volatile memory that can have defective rows and columns. Redundant rows and columns are redirected to in lieu of the defective rows and columns. Redundant circuitry is used to determine if an address is a defective address stored in register 40 by seeing if they match. An error code (mask) is appended to the defective address.).
Claims 11-17 are the device claims to method claims 1-5, 8 and 9 above and are rejected in the same manner utilizing the same rationale.
Claim 19 is the program product claim to method claim 1 above and is rejected in the same manner utilizing the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abedifard et al. (US 2004/0160826) as applied to claims 1, 11 and 19 above, and further in view of official notice.
Consider claim 10, Abedifard et al. discloses the use of NVM devices, but does not discloses that these devices are phase change memories. PCM devices consume less power during write operations and almost no power in idle states, have high memory cell density and can tolerate a high number of write cycles. PCM devices are well known memory devices with distinct known advantages and therefore the examiner is taking official notice to their use when NVM devices are used.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the NVM device of Abedifard et al. to be PCM device because PCM devices consume less power during write operations and almost no power in idle states, have high memory cell density and can tolerate a high number of write cycles due to its phase change mechanisms.
Claim 18 is the device claim to method claim 10 above and is rejected in the same manner utilizing the same rationale.
Claim 20 is the program product claim to method claim 10 above and is rejected in the same manner utilizing the same rationale.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2139
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