Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 7-10, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over KIM GWANG HYEON (KR 20040035484 A), hereinafter KIM, in view of Narey et al. (United States Patent US 9250919), hereinafter Narey.
Regarding claim 1, KIM teaches a system comprising: a memory device; and a processing device, operatively coupled with the memory device (Page 2 “a CPU, a memory,…The memory includes a RAM, a BIOS ROM, a COMS RAM…”), to perform operations comprising: receiving, from a host system connected to the memory device, a first reset signal (Page 6 “In accordance with the user's selection of the boot selector 3 or 5, power is applied to the computer system (S10).”);
responsive to determining that the first value indicates the fast boot, loading a fast boot firmware from the memory device, wherein the fast boot firmware allows the processing device to access a boot partition of the memory device; and responsive to receiving a request from the host system, retrieving boot data from the boot partition (Page 4 “The boot controller 1 executes a boot mode according to the quick boot selector 5 or the general boot selector 3…When the quick boot selection unit 5 is selected, the boot control unit 1 loads the system configuration data stored in the system component storage unit 10 so that the system configuration of the current system unit 1 is the system configuration when the previous system is used.” Page 5 “The BIOS ROM 29 stores a general BIOS program 30 commonly used in a computer system and a quick boot BIOS program 32 executed in a quick boot mode…The quick boot BIOS program 32 may shorten the booting time by omitting some processes during initial booting. The quick boot BIOS program 32 initializes the main chipset of the system unit 20, immediately loads system configuration data stored in the CMOS RAM 34... when the quick boot selection unit 25 is selected, the boot control unit 20 loads the fast boot BIOS program 32 stored in the BIOS ROM 29 to be booted. When the fast boot BIOS is loaded and executed by the boot controller 20, the BIOS initializes the main chipset, skips POST on system components, and immediately loads system configuration data stored in the CMOS RAM 34.” A quick boot is selected by a user. Then, a signal or value indicating the quick boot is interpreted as the first value indicates the fast boot. When the quick boot is selected, a quick boot BIOS program is selected, loaded from a BIOS ROM, and executed, which is interpreted as loading a fast boot firmware from the memory device. BIOS is a type of firmware. When the quick boot BIOS program is executed, the system configuration data stored in the COMS RAM is accessed.).
However, KIM does not explicitly teach determining whether a first value stored in a configuration space of the memory device indicates a fast boot.
Narey teaches determining whether a first value stored in a configuration space of the memory device indicates a fast boot ([Col. 10 Lines 28-36] “At operation 304B, user-specified settings might be utilized to select the firmware 137 for use in booting and operating the computer 100… Data identifying the selected firmware 13 7 might be stored in the NVRAM area 206A and retrieved at boot time. The data can then be utilized to select the firmware 137 that should be utilized to boot and operate the computer 100.” [Col. 11 Lines 53-56] “FIG. 4A shows one configuration of the single memory device 126 in which a firmware image 137A for a fast-boot firmware and a firmware image 137B for a full functionality firmware have been stored therein.” Data identifying the selected firmware is interpreted as a first value stored in a configuration space of the memory device. Furthermore, the selected firmware includes a fast-boot firmware.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of KIM by incorporating the teaching of Narey of determining whether a first value stored in a configuration space of the memory device indicates a fast boot. They are all directed toward the fast booting using a fast boot firmware. As well known in the art before the effective filing date of the claimed invention, a value stored in a memory device is a data or collections of bits stored in the memory. Combining two well known methods, such as determining the fast booting process and using the value stored in the memory for the determination step is well known in the art before the effective filing date of the claimed invention and obvious to combine two well-known methods.
Regarding claim 2, KIM in view of Narey teaches all the limitations of the system of claim 1, as discussed above.
KIM, as modified above, further teaches performing, using a second value stored in the configuration space of the memory device, a first training of one or more first connection lanes between the memory device and the host system (Page 4 “When the quick boot selection unit 5 is selected, the boot control unit 1 loads the system configuration data stored in the system component storage unit 10 so that the system configuration of the current system unit 1 is the system configuration when the previous system is used.” The system configuration during the booting process is to initialize or configure various components of the system including connection between components. Therefore, by configuring the system using the system configuration data stored in the system configuration component storage unit, the connection between the memory device and the host system is configured or trained. As discussed above, a value stored in a memory device is a data or collections of bits stored in the memory.).
Regarding claim 7, KIM in view of Narey teaches all the limitations of the system of claim 1, as discussed above.
Narey further teaches wherein the host system is connected to the memory device via a peripheral component interconnect express (PCIe) link, and wherein the fast boot firmware comprises boot partition support features that includes peripheral component interconnect express (PCIe) interface functionality (FIG. 1 “PCI BUS” [Col. 6 Lines 18-19] “the bus comprises a peripheral component interconnect ("PCI") bus.” The PCI bus connects components including a CPU, memory, and other components, which executes the booting process.).
Regarding claim 8, KIM in view of Narey teaches all the limitations of the system of claim 1, as discussed above.
KIM, as modified above, further teaches wherein the memory device comprises a non-volatile memory (Page 2 “a CPU, a memory,…The memory includes a RAM, a BIOS ROM, a COMS RAM…”).
Regarding claim(s) 9, 10, 14, and 15, the claim(s) 9, 14, and 15 are the method claims of the apparatus claim(s) 1, 2, 7, and 8. The claim(s) 9, 14, and 15 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, KIM in view of Narey teaches all the limitations of the claim(s) 9, 14, and 15.
Regarding claim(s) 16 and 17, the claim(s) 16 and 17 are the non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations claims of the apparatus claim(s) 1 and 2. Narey further teaches the non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations ([Col. 6 Lines 48-53] “Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for the non-transitory storage of information such as computer-readable instructions, data structures, program modules or other data.”). The claim(s) 16 and 17 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, KIM in view of Narey teaches all the limitations of the claim(s) 16 and 17.
Claim(s) 3-6, 11-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Narey as applied to claims 1, 2, 9, 10, 16, and 17 above, and further in view of Nair et al. (United State Patent Application Publication US 2016/0283433), hereinafter Nair.
Regarding claim 3, KIM in view of Narey teaches all the limitations of the system of claim 2, as discussed above.
However, KIM in view of Narey does not explicitly teach wherein the second value indicates at least one of: a first data rate representing a link speed less than a maximum link speed, or a first number of connection lanes representing a link width less than a maximum link width.
Nair teaches wherein the second value indicates at least one of: a first data rate representing a link speed less than a maximum link speed, or a first number of connection lanes representing a link width less than a maximum link width ([0033] “Note that PCIe interfaces in a node typically receive programming (e.g., by Basic Input Output System (BIOS)) after reset to configure the ports with proper widths and speeds, to enable a link to train and function properly… this link may be configured at x4 or x4 width at PCIe Gen1 speed 4 (which is at a link width of 4 or 1 and an operating frequency of 2.5 GHz). After initial operations at this base link width and speed, BIOS or other boot code (e.g., stored in an eSPI device) may operate to re-initialize the designated PCIe interface to a higher level of functionality.” The width and speed of PCIe interfaces are trained during the initialization or after the reset. Nair further teaches to reconfigure the PCIe interfaces to a higher level of functionality. Thus, Nair suggests that the initial configuration of the PCIe interface before the reconfiguration is less than the maximum functionality.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of KIM in view of Narey by incorporating the teaching of Nair of wherein the second value indicates at least one of: a first data rate representing a link speed less than a maximum link speed, or a first number of connection lanes representing a link width less than a maximum link width. They are all directed toward configurating a system during a booting process. As recognized by Nair, in multi-node systems, some amount of platform resource sharing occurs ([0003]). By configuring connections or links between nodes or components to a low level during initialization, congestion or overcrowding for sharing resources can be prevented. Therefore, it would be advantageous to incorporate the teaching of Nair of wherein the second value indicates at least one of: a first data rate representing a link speed less than a maximum link speed, or a first number of connection lanes representing a link width less than a maximum link width in order to improve a stability of the system by controlling limited resources.
Regarding claim 4, KIM in view of Narey teaches all the limitations of the system of claim 1, as discussed above.
KIM further teaches responsive to determining that the first value does not indicate the fast boot, loading a normal boot firmware from the memory device, wherein the normal boot firmware allows the processing device to have full operational access to the memory device (Page 4 “The boot controller 1 executes a boot mode according to the quick boot selector 5 or the general boot selector 3. When the general boot selection unit 3 is selected, the boot control unit 1 loads the BIOS from the BIOS memory and performs a POST for testing each component of the system unit 1.” Page 5 “During the POST, the BIOS initializes and tests each system device by comparing the system configuration data obtained from the POST with the system configuration data stored in the CMOS RAM 34.” When the general boot mode is selected, POST, which is skipped during the quick boot, is executed including accessing the system configuration data for comparison and test.); and
performing, using a third value stored in the configuration space of the memory device, a second training of one or more second connection lanes between the memory device and the host system (Page 4 “When the quick boot selection unit 5 is selected, the boot control unit 1 loads the system configuration data stored in the system component storage unit 10 so that the system configuration of the current system unit 1 is the system configuration when the previous system is used.” The system configuration during the booting process is to initialize or configure various components of the system including connection between components. Therefore, by configuring the system using the system configuration data stored in the system configuration component storage unit, the connection between the memory device and the host system is configured or trained. As discussed above, a value stored in a memory device is a data or collections of bits stored in the memory.).
Nair further teaches wherein the third value indicates at least one of: a second data rate representing a maximum link speed, or a second number of connection lanes representing a maximum link width ([0033] “Note that PCIe interfaces in a node typically receive programming (e.g., by Basic Input Output System (BIOS)) after reset to configure the ports with proper widths and speeds, to enable a link to train and function properly… this link may be configured at x4 or x4 width at PCIe Gen1 speed 4 (which is at a link width of 4 or 1 and an operating frequency of 2.5 GHz). After initial operations at this base link width and speed, BIOS or other boot code (e.g., stored in an eSPI device) may operate to re-initialize the designated PCIe interface to a higher level of functionality.” A higher level of functionality of the PCIe interface is higher level of width and speed of the PCIe. Nair suggests that the higher level of the functionality is greatest or highest amount that the PCIe is allowed for a selected configuration.).
Regarding claim 5, KIM in view of Narey teaches all the limitations of the system of claim 1, as discussed above.
KIM, as modified above, further teaches receiving a second reset signal; determining whether the modified first value indicates a normal boot; responsive to determining that the modified first value indicates the normal boot, loading a normal boot firmware from the memory device, wherein the normal boot firmware allows the processing device to have full operational access to the memory device (Page 4 “The boot controller 1 executes a boot mode according to the quick boot selector 5 or the general boot selector 3. When the general boot selection unit 3 is selected, the boot control unit 1 loads the BIOS from the BIOS memory and performs a POST for testing each component of the system unit 1.” Page 5 “During the POST, the BIOS initializes and tests each system device by comparing the system configuration data obtained from the POST with the system configuration data stored in the CMOS RAM 34.” When the general boot mode is selected, POST, which is skipped during the quick boot, is executed including accessing the system configuration data for comparison and test.).
Narey further teaches modifying, in a configuration space of the memory device, the first value to indicate a normal boot ([Col. 10 Lines 28-36] “At operation 304B, user-specified settings might be utilized to select the firmware 137 for use in booting and operating the computer 100…Data identifying the selected firmware 13 7 might be stored in the NVRAM area 206A and retrieved at boot time. The data can then be utilized to select the firmware 137 that should be utilized to boot and operate the computer 100.” [Col. 11 Lines 53-56] “FIG. 4A shows one configuration of the single memory device 126 in which a firmware image 137A for a fast-boot firmware and a firmware image 137B for a full functionality firmware have been stored therein.” Narsey suggests to select one of two firmware, such as a fast-boot firmware and a full functionality firmware during the booting process, based on the data stored in the NVRAM. Thus, Narsey suggests the data identifying the firmware to select during the booting process is modified.).
Nair teaches performing, using one or more values representing a maximum link speed and a maximum link width, a second training of one or more second connection lanes ([0033] “Note that PCIe interfaces in a node typically receive programming (e.g., by Basic Input Output System (BIOS)) after reset to configure the ports with proper widths and speeds, to enable a link to train and function properly… this link may be configured at x4 or x4 width at PCIe Gen1 speed 4 (which is at a link width of 4 or 1 and an operating frequency of 2.5 GHz). After initial operations at this base link width and speed, BIOS or other boot code (e.g., stored in an eSPI device) may operate to re-initialize the designated PCIe interface to a higher level of functionality.” A higher level of functionality of the PCIe interface is higher level of width and speed of the PCIe. Nair suggests that the higher level of the functionality is greatest or highest amount that the PCIe is allowed for a selected configuration.).
Regarding claim 6, Kim in view of Narey and further in view of Nair teaches all the limitations of the system of claim 5, as discussed above.
Narey further teaches modifying the modified first value to a default value indicating the fast boot ([Col. 10 Lines 28-36] “At operation 304B, user-specified settings might be utilized to select the firmware 137 for use in booting and operating the computer 100…Data identifying the selected firmware 13 7 might be stored in the NVRAM area 206A and retrieved at boot time. The data can then be utilized to select the firmware 137 that should be utilized to boot and operate the computer 100.” [Col. 11 Lines 53-56] “FIG. 4A shows one configuration of the single memory device 126 in which a firmware image 137A for a fast-boot firmware and a firmware image 137B for a full functionality firmware have been stored therein.” Narsey suggests to select one of two firmware, such as a fast-boot firmware and a full functionality firmware during the booting process, based on the data stored in the NVRAM. Thus, Narsey suggests the data identifying the firmware to select during the booting process is modified.).
Regarding claim(s) 11-13, the claim(s) 11-13 are the method claims of the apparatus claim(s) 3, 5, and 6. The claim(s) 11-13 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, KIM in view of Narey and further in view of Nair teaches all the limitations of the claim(s) 11-13.
Regarding claim(s) 18-20, the claim(s) 18-20 are the non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations claims of the apparatus claim(s) 3, 5, and 6. Narey further teaches the non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations ([Col. 6 Lines 48-53] “Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for the non-transitory storage of information such as computer-readable instructions, data structures, program modules or other data.”). The claim(s) 18-20 does(do) not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, KIM in view of Narey and further in view of Nair teaches all the limitations of the claim(s) 18-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ganesan et al. (Unites States Patent Application Publication US 2020/021852) teaches a BMC to notify an OS system of the IHS of receipt of a firmware update for a PCI component and BIOS to perform a quick boot based on a boot flag to determine whether to perform a quick boot.
Srivastava et al. (Unites States Patent Application Publication US 2021/0294772) teaches a firmware agent to execute a first firmware and a boot agent coupled to a PCIe interface to download the PCIe firmware.
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/HYUN SOO KIM/Examiner, Art Unit 2176
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