DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al (US20170162542) hereinafter Chen.
As to clam 1, Chen discloses an apparatus comprising: a substrate (Fig.1J, and substrate 52) ; a first die on the substrate, the first die including a plurality of memory units (Fig. 1J and module 12); a second die over the first die, the second die including a plurality of processing units (Fig. 1J and module 10, para. 0015); a first stack of memory dies on the substrate and positioned adjacent to the first die and the second die (Fig. 1J, and module 12, para. 0015); and a second stack of memory dies on the substrate and positioned adjacent to the first die and the second die, the first die and the second die are between the first stack of memory dies and the second stack of memory dies (Fig. 1J where a plurality of memory stacks (modules 12) and other devices (modules 10), para. 0015).
As to claim 2, Chen discloses the apparatus further comprising: a third stack of memory dies on the substrate and positioned adjacent to the first die and the second die, and the first stack of memory dies (Fig. 1J shows a system a system of a plurality of modules supporting multiple SoC stacked dies, and supporting a plurality of embodiment, para. 0015).
As to claim 3, Chen discloses the apparatus further comprising: a fourth stack of memory dies on the substrate and positioned adjacent to the first die and the second die, and the second stack of memory dies (Fig. 1J shows a system a system of a plurality of modules supporting multiple SoC stacked dies, and supporting a plurality of embodiment, para. 0015).
As to claim 4, Chen discloses the apparatus, wherein the substrate is an interposer (Fig. 1J, module 18, para. 0016).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen view of Wuu et al (US20190129651) hereinafter Wuu.
As to claim 5, Chen does not explicitly disclose the apparatus, wherein the first stack of memory dies and the second stack of memory dies are coupled to the first die via a memory controller interface.
Wuu teaches the apparatus, wherein the first stack of memory dies and the second stack of memory dies are coupled to the first die via a memory controller interface (Fig. 1, and para. 0018). One of ordinary skill in the art before the effective filing date of the claim invention would have been motivated to use the controller of Wuu with the plurality memory stacks of Chen to enable an efficient connection between the compute, and memory modules of the stacks, paras. 0001).
As to claim 6, Wuu discloses the apparatus, wherein an individual memory unit of the plurality of memory units is vertically aligned with an individual processing unit of the plurality of processing units (Fig. 1, and para. 0010, where a vertical stack of compute and memory dies are taught). One of ordinary skill in the art before the effective filing date of the claim invention would have been motivated to use the controller of Wuu with the plurality memory stacks of Chen to enable an efficient connection between the compute, and memory modules of the stacks, paras. 0001).
As to claim 16, Wuu discloses the apparatus, wherein the first die includes one of a FE-RAM, DRAM, or an SRAM (Fig. 1, and para. 0010). One of ordinary skill in the art before the effective filing date of the claim invention would have been motivated to use the controller of Wuu with the plurality memory stacks of Chen to enable an efficient connection between the compute, and memory modules of the stacks, paras. 0001).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Wuu as applied to claim 1 above, and further in view of Takanashi et al (JP2004-315268 a) hereinafter Takanashi.
As to claim 7, Chen as modified by Wuu does not explicitly disclose the apparatus, wherein the individual memory unit comprises non-linear polar material.
Takanashi teaches wherein the individual memory unit comprises non-linear polar material (para. 0002). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the details of materials top facilitate the production of RAM tile for the combination
Claims 8, 11- 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Wuu in further view of Lau et al (WO 2018/126073 A1) hereinafter Lau in further view of Brewer (US 10,461,076).
As to claims 8, and 12, Chen/Wuu does not explicitly disclose the apparatus, wherein the individual processing unit comprises: a matrix multiplier communicatively coupled to the individual memory unit; and a buffer communicatively coupled to the individual memory unit.
Lau teaches apparatus comprising: a first die [high bandwidth memory (HBM) stacked
dies 310a-d are provided, but not on the same silicon die as the DLH device 205" in
para. 0053; HIGH BANDWIDTH MEMORY 1640a-1640d in fig. 16B) including a
plurality of a random-access memory (RAM) tiles to store input data, weight factors, and
outputs ( "High bandwidth memory (HBM) modules 1640 may be memory
components associated with matrix processing chip 1620 that are used to store matrix
operands and other matrix data. In some embodiments, high bandwidth memory (HBM)
modules 1640 may be designed to efficiently store and retrieve matrix data" in
para. 0092); and a second die, wherein the second die includes a plurality of compute tiles [e.g., CLUSTER 1630a-1630 in fig. 16B; "Matrix processing clusters 1630 may include processing resources configured to perform matrix operations, such as matrix multiplication, convolutions, and/or dimension shuffling, among other examples" in para. 0093], wherein individual compute tile includes:
a matrix multiplier [e.g., 32x32 MULTIPLIER CORE 915 in fig. 9; "Matrix
Processing Units (MPU) 810 may represent the primary data computation engine of an
example DLH device and its processing cluster(s). Each cluster may contain two or
more instances of the MPU, which may be independently controlled. In some
implementations, a MPU may be optimized for matrix-matrix multiplication operations" in
paragraph 0063] communicatively coupled to one or more RAM tiles of the first die [e.g.,
"An on-chip fabric 605 may be used to interconnect the DHL processing clusters
(which, in turn, may connect to HBMs (e.g., 320a-d))" in paragraph 0056; figs. 5, 6]; and
a buffer (e.g., MEMORY RESOURCE BLOCKS 1638 in fig. 16B; "Read engine
1735 may then store the matrix data retrieved from H BM 1740a in certain MRBs 1738a
of its associated cluster" in paragraph 0113) communicatively coupled to the one or
more RAM tiles of the first die.
Lau also teaches the second die in communication with the first die, however, Lau
do not explicitly teach the second die over the first die.
Brewer teaches the second die over the first die, wherein the individual compute tile is substantially vertically aligned with an individual RAM tile of the plurality of RAM tiles [e.g., Processing Logic Die 106 over Volatile Memory Die 108, Non-volatile Memory Die 104 in fig. 1; "FIG. 4 illustrates a top view of the processing logic die 106 die 106 having multiple processing logic partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i in accordance with some embodiments of the present disclosure. FIG. 4 shows each of the partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i having a separate FPGA 406" in col. 7, line 65-col. 8, line 3; "Each of the partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i has multiple volatile memory elements. Each of the partitions illustrated in FIG. 3 shows nine volatile memory element clusters 306. And, each of the volatile memory element clusters 306 shows nine volatile memory elements 308" in col. 7, lines 45-50; fig. 5].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen/Wuu/Lau to implement Brewer's teaching above including wherein the individual compute tile is substantially vertically aligned with an individual RAM tile of the plurality of RAM tiles including non-linear polar material in order to increase efficiency in packaging, lower power usage, and/or faster communications in the dies of Lau (e.g., "A 3D IC is an integrated circuit built by stacking silicon dies and interconnecting them vertically so that a combination of the dies is a single device. With a 3D IC, electrical paths through the device can be shortened by its vertical layout, which creates a device that can be faster and has a smaller footprint than similar ICs arranged side-by-side" in col. 1, lines 43-48 of Brewer).
As to claims 11, 13, and 14, Lau discloses the apparatus comprising a ring or mesh interconnect that is coupled to the first die and the second die (Fig. 5, and para. 0053). One of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen/Wuu to enable increased efficiency in packaging of modules, thus lowering power, and enabling faster module communication.
As to claim 15, Wuu discloses the apparatus, wherein the first and second interconnects extend vertically between the first and second dies (Fig. 1, and para. 0012). One of ordinary skill in the art before the effective filing date of the claim invention would have been motivated to use the controller of Wuu with the plurality memory stacks of Chen to enable an efficient connection between the compute, and memory modules of the stacks, paras. 0001).
Allowable Subject Matter
Claims 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance: Independent claim 17 and its dependents thereof are allowed because the prior art either alone or in combination fail to anticipate or render obvious, the claimed limitation of
“ the third die including a second plurality of memory units, the third die adjacent to the first die; a fourth die over the third die, the second die including a second plurality of processing units, the fourth die adjacent to the second die; a first stack of memory dies on the interposer and positioned adjacent to the first die and the second die; and a second stack of memory dies on the interposer and positioned adjacent to the third die and the fourth die, the first die, the second die, the third die, and the fourth die are between the first stack of memory dies and the second stack of memory dies.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US11152343, US20170109063, US20190198489, among others teach 3D package module device arrangements with memory and processors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER ANTHONY DALEY whose telephone number is (571)272-3625. The examiner can normally be reached 7 - 3:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571 2724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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