Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Applicant’s Response filed June 7, 2026 is acknowledged.
- no claim(s) is/are amended
- Claim(s) 10-13 is/are withdrawn as non-elected
- Claim(s) 1-20 is/are pending in the application.
- Claim(s) 1-9, 14-20 is/are examined on the merits
Election/Restrictions
Applicant’s election without traverse of Species I of Figure 2 in the reply filed on June 7, 2026 is acknowledged.
Claims 10-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 7, 2026.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 4, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Awakura et al, U.S. Patent Publication No. 20070291021.
Consider claim 15, Awakura teaches a display driving circuit for driving a pixel array that displays an image (see Awakura paragraph 0027-0029 where although a liquid crystal display device is described as one example of the active-matrix display device, it is applicable to other display devices such as organic EL display), the display driving circuit comprising:
an interface circuit configured to receive commands and image data from a host processor (see Awakura figure 1, element 105, 104 and paragraphs 0030-0036 where An update command of partial-display data is inputted to the system interface 105 from the MPU 104 at the time of display-data update of the partial-display data, and the partial-display data is once stored in the partial memory 110 according to an address control of the address counter 108),
receive a first command of the commands and first frame data corresponding to a first image of one frame of the image data in a first frame period (see Awakura figure 3A, element 201-a), and receive a second command of the commands and partial update data corresponding to a partial area of a second image of one frame of the image data in a second frame period (see Awakura figure 3C, element 201-b);
a row driving circuit configured to enable at least one update row from among a plurality of rows of the pixel array during a data write period of the second frame period (see Awakura figure 1, element 103); and
a data driving circuit configured to provide the partial update data to at least one update column from among a plurality of columns of the pixel array, based on the partial update data during the data write period of the second frame period (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed and paragraphs 0051-0062 specifically for example paragraph 0051 where FIG. 3A shows a partial display before update, FIG. 3B shows a partial display during data transfer with the partial-display area updated from 201-a to 201-b, and FIG. 3C shows a partial-display after update. Note that, correspondingly, the non-partial-display area is updated from 205-a to 205-b.).
Consider claim 16, Awakura teaches all the limitations of claim 15 and further teaches wherein: the interface circuit is configured to receive the partial update data during at least one horizontal period from among a plurality of horizontal periods in the data write period of the second frame period, and the row driving circuit is configured to enable the at least one update row during the at least one horizontal period (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed and figure 2B where horizontal synchronizing timing corresponds to rows being written with display data).
Consider claim 17, Awakura teaches all the limitations of claim 15 and further teaches wherein, during a data write period of the first frame period: the row driving circuit is configured to sequentially enable a plurality of rows of the pixel array, and the data driving circuit is configured to provide the first frame data to the plurality of columns of the pixel array (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed and figure 2B where horizontal synchronizing timing corresponds to rows being written with display data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Awakura et al, U.S. Patent Publication No. 20070291021 in view of Cok, U.S. Patent Publication No. 20230196979
Consider claim 1, Awakura teaches a display driving circuit comprising: a pixel circuit array including a plurality of pixel circuits arranged in a matrix, each of the plurality of pixel circuits (see Awakura paragraph 0027-0029 where although a liquid crystal display device is described as one example of the active-matrix display device, it is applicable to other display devices such as organic EL display)
an interface circuit configured to receive a partial update command and partial update data from a host processor (see Awakura figure 1, element 105, 104 and paragraphs 0030-0036 where An update command of partial-display data is inputted to the system interface 105 from the MPU 104 at the time of display-data update of the partial-display data, and the partial-display data is once stored in the partial memory 110 according to an address control of the address counter 108);
a control logic configured to generate a first update area signal indicating at least one update row including update pixel circuits to which the pixel data is to be updated from among a plurality of rows of the pixel circuit array, based on update area information included in the partial update command (see Awakura paragraphs 0035-0040 specifically for example paragraph 0037 where address counter 108 updates the display data by an address control of the memory according to settings of partial-display area stored in the setting register 106, for example, as shown in FIG. 2A, information capable of distinguishing the area like coordinates of the upper-left point (origin 203) and the bottom-right point (end-point 204) of the rectangular area with respect to the whole display area or an origin and a size of the area (height, width), and position information of pixels to be updated and display data);
a row driving circuit configured to provide write clock signals to first pixel circuits included in the at least one update row of the pixel circuit array, based on the first update area signal (see Awakura figure 1, element 103); and
a data driving circuit configured to provide update pixel data to each of the update pixel circuits from among the first pixel circuits, based on the partial update data (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed).
Awakura teaches the invention is applicable to other display devices such as organic EL display. However, Awakura is silent regarding configured to store pixel data and provide a driving current corresponding to the pixel data to an emission device.
In a related field of endeavor, Cok teaches organic light-emitting diode (OLED) displays rely on passing current through a layer of organic material that glows in response to the current (see Cok paragraph 0003, 0015, 0079, 0089). Cok further teaches active-matrix pixels having pixel memory so as to store pixel data when implementing an OLED display (see Cok paragraph 0079 where Pixel memory 26 can be a digital memory (e.g., an SRAM or shift register storing digital values representing the desired brightness of each light-emitting diode 50) or an analog memory (e.g., one or more capacitors storing a charge representing the desired brightness of each light-emitting diode 50).)
One of ordinary skill would have been motivated to have modified Awakura with the teachings of Cok to have an active matrix OLED display configured to store pixel data and provide a driving current corresponding to the pixel data to an emission device so as to implement an OLED display device using known techniques with predictable results.
Consider claim 2, Awakura as modified by Cok teaches all the limitations of claim 1 and further teaches wherein during a data write period in one frame period: the interface circuit is configured to receive the partial update data (see Awakura figure 1, element 105, 104 and paragraphs 0030-0036 where An update command of partial-display data is inputted to the system interface 105 from the MPU 104 at the time of display-data update of the partial-display data, and the partial-display data is once stored in the partial memory 110 according to an address control of the address counter 108), and
the data driving circuit is configured to provide the update pixel data to each of the update pixel circuits, based on the partial update data (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed).
Consider claim 3, Awakura as modified by Cok teaches all the limitations of claim 2, wherein: the interface circuit is configured to receive row data corresponding to the at least one update row in at least one horizontal period corresponding to the at least one update row among a plurality of horizontal periods included in the data write period, and the row data includes pixel data corresponding to each of non-update pixel circuits from among the first pixel circuits and the partial update data (see Awakura figures 2A-2B and paragraphs 0035-0041 specifically for example paragraph 0040 where partial-display data is transferred by the MUX 111 matching the timing of the partial-display area 201. At the display timing of the area other than the partial-display area (hereinafter, referred to as non-partial-display area 205), the background color data set in the setting register 106 is inserted).
Consider claim 9, Awakura as modified by Cok teaches all the limitations of claim 1 and further teaches wherein the control logic is further configured to: generate a second update area signal indicating at least one column including the update pixel circuits from among a plurality of columns of the pixel circuit array, based on the update area information, and provide the second update area signal to the data driving circuit (see Awakura figures 3A-3C, element 201-a, 205-B).
Consider claim 14, Awakura as modified by Cok teaches all the limitations of claim 1 and further teaches wherein the emission device includes a light- emitting diode (LED) having a size of the LED being 100 micrometers (pm) or less (see Cok paragraph 0013 where each pixel can comprise one or more inorganic micro-light-emitting-diodes. Each inorganic micro-light-emitting-diodes can have a length and width no greater than 200 microns, no greater than 100 microns, no greater than 50 microns, no greater than 20 microns, no greater than 10 microns, no greater than 5 microns, or no greater than 3 microns).
Claim(s) 4-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Awakura et al, U.S. Patent Publication No. 20070291021 and Cok, U.S. Patent Publication No. 20230196979 in view of Sakariya et al, U.S. Patent Publication No. 20140104243
Consider claim 4, Awakura as modified by Cok teaches all the limitations of claim 2 and further teaches wherein: the interface circuit is configured to receive row data corresponding to the at least one update row (see Awakura figures 2A-2B and paragraphs 0035-0041 specifically for example figure 2 where display data is provided row by row according to horizontal synchronizing timing).
Awakura is silent regarding the row data includes the partial update data in at least one horizontal period that is relatively earlier from among a plurality of horizontal periods included in the data write period.
In the same field of endeavor, Sakariya teaches various different update options including the row data includes the partial update data in at least one horizontal period that is relatively earlier from among a plurality of horizontal periods included in the data write period (see Sakariya figure 4B where idle periods complete the frame interval and paragraph 0047 where Instead of being idle in the line cycles of R.sub.3 and R.sub.4, the scan driver 124 proceeds to select the next rows following R.sub.3 and R.sub.4. As shown in FIG. 4A, the line cycle that was scheduled for refreshing R.sub.3 is now used for refreshing R.sub.5, which is the next row following R.sub.3 and R.sub.4 that has a content change.) so as to reduce power consumption.
One of ordinary skill would have been motivated to have modified Awakura with the teachings of Sakariya to have row data including the partial update data in at least one horizontal period that is relatively earlier from among a plurality of horizontal periods included in the data write period so as to reduce power consumption using known techniques with predictable results.
Consider claim 5, Awakura as modified by Cok and Sakariya teaches all the limitations of claim 4 and further teaches wherein the row data includes pixel data corresponding to each of non-updated pixel circuits among the first pixel circuits and the partial update data (see Awakura figures 2A-2B and paragraphs 0035-0041 specifically for example paragraph 0040 where partial-display data is transferred by the MUX 111 matching the timing of the partial-display area 201. At the display timing of the area other than the partial-display area (hereinafter, referred to as non-partial-display area 205), the background color data set in the setting register 106 is inserted).
Consider claim 6, Awakura as modified by Cok and Sakariya teaches all the limitations of claim 4 and further teaches wherein the row data includes the partial update data except for pixel data corresponding to non-updated pixel circuits among the first pixel circuits (see Sakariya figure 4B where idle periods complete the frame interval and paragraph 0047 where Instead of being idle in the line cycles of R.sub.3 and R.sub.4, the scan driver 124 proceeds to select the next rows following R.sub.3 and R.sub.4. As shown in FIG. 4A, the line cycle that was scheduled for refreshing R.sub.3 is now used for refreshing R.sub.5, which is the next row following R.sub.3 and R.sub.4 that has a content change.).
Consider claim 7, Awakura as modified by Cok and Sakariya teaches all the limitations of claim 6 and further teaches wherein: the partial update data corresponds to two or more update rows of the pixel circuit array, and the partial update data is received in units of rows during two or more relatively preceding horizontal periods among the plurality of horizontal periods (see Sakariya figure 4B where idle periods complete the frame interval and paragraph 0047 where Instead of being idle in the line cycles of R.sub.3 and R.sub.4, the scan driver 124 proceeds to select the next rows following R.sub.3 and R.sub.4. As shown in FIG. 4A, the line cycle that was scheduled for refreshing R.sub.3 is now used for refreshing R.sub.5, which is the next row following R.sub.3 and R.sub.4 that has a content change.).
Consider claim 8, Awakura as modified by Cok and Sakariya teaches all the limitations of claim 6 and further teaches wherein: the partial update data corresponds to two or more update rows of the pixel circuit array, and first update data corresponding to at least two update rows among the partial update data is received during the most preceding horizontal period among the plurality of horizontal periods (see Sakariya figure 4B where idle periods complete the frame interval and paragraph 0047 where Instead of being idle in the line cycles of R.sub.3 and R.sub.4, the scan driver 124 proceeds to select the next rows following R.sub.3 and R.sub.4. As shown in FIG. 4A, the line cycle that was scheduled for refreshing R.sub.3 is now used for refreshing R.sub.5, which is the next row following R.sub.3 and R.sub.4 that has a content change.).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Awakura et al, U.S. Patent Publication No. 20070291021 in view of Sakariya et al, U.S. Patent Publication No. 20140104243
Consider claim 18, Awakura teaches all the limitations of claim 15 and further teaches wherein: the interface circuit is configured to receive a third command of the commands from the host processor during a third frame period (implicit see Awakura figure 3C, element 201-b it is implicit that any number of partial display update area for any number of frames are contemplated for image display),
Awakura is silent regarding the row driving circuit is configured to disable the plurality of rows of the pixel array during a data write period of the third frame period.
In the same field of endeavor, Sakariya teaches various different update options including the row driving circuit configured to disable the plurality of rows of the pixel array during a data write period of the third frame period (see Sakariya figure 4B where idle periods complete the frame interval and paragraph 0047 where Instead of being idle in the line cycles of R.sub.3 and R.sub.4, the scan driver 124 proceeds to select the next rows following R.sub.3 and R.sub.4. As shown in FIG. 4A, the line cycle that was scheduled for refreshing R.sub.3 is now used for refreshing R.sub.5, which is the next row following R.sub.3 and R.sub.4 that has a content change. And figure 4A where R3, R4 are skipped) so as to reduce power consumption.
One of ordinary skill would have been motivated to have modified Awakura with the teachings of Sakariya to have row driving circuit configured to disable the plurality of rows of the pixel array during a data write period of the third frame period so as to reduce power consumption using known techniques with predictable results.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwa et al, U.S. Patent Publication No. 20190041955 in view of Awakura et al, U.S. Patent Publication No. 20070291021.
Consider claim 19, Kwa teaches an operation method of a display driving circuit for driving a pixel array that displays an image, the operation method comprising: fully updating frame data stored in the pixel array with first frame data corresponding to a first image, based on a first command received from a host processor and the first frame data, during a data write period of a first frame period (see Kwa figure 4, element Full Frame Update); and
partially updating frame data stored in the pixel array with partial update data, based on a second command received from the host processor and the partial update data, during a data write period of a second frame period (see Kwa figure 4, element Partial Frame N’, Partial Frame N+2’),
Kwa is silent regarding wherein the partially updating of the frame data comprises: receiving the partial update data in at least one horizontal period from among a plurality of horizontal periods in the data write period of the second frame period; and writing the partial update data to at least one update row of a plurality of rows of the pixel array during the at least one horizontal period.
In the same field of endeavor, Awakura teaches partially updating of the frame data comprises: receiving the partial update data in at least one horizontal period from among a plurality of horizontal periods in the data write period of the second frame period; and writing the partial update data to at least one update row of a plurality of rows of the pixel array during the at least one horizontal period (see Awakura figure 1, element 117 and paragraph 0034 where display data is converted to accommodate alternate current, and data for one display line is: buffered in the fetching latch 115; synchronized with scanning timing of the gate driver 113 by the synchronizing latch 116; and converted to an analog voltage from digital data to drive the data line in the DAC 117, and then the display data is displayed and figure 2B where horizontal synchronizing timing corresponds to rows being written with display data) so as to partially update display data in synchronization with timing signals.
One of ordinary skill would have been motivated to have modified Kwa with the teachings of Awakura to have partially updating of frame data comprising: receiving the partial update data in at least one horizontal period from among a plurality of horizontal periods in the data write period of the second frame period; and writing the partial update data to at least one update row of a plurality of rows of the pixel array during the at least one horizontal period as disclosed by Awakura so as to partially update display data in synchronization with timing signals using known techniques with predictable results.
Consider claim 20, Kwa as modified by Awakura teaches all the limitations of claim 19 and further teaches further comprising: self-refreshing frame data stored in the pixel array, based on a third command received from the host processor during a data write period of a third frame period (see Kwa figure 4, element PSR and paragraphs 0016-0017 where when the panel 18 is operating in a self-refresh mode, sometimes referred to as panel self-refresh (PSR).).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lai et al, U.S. Patent Publication No. 20110018857 (figures 2-4), Kim et al, U.S. Patent Publication No. 20140104327 (reducing power consumption), Wyatt et al, U.S. Patent Publication No. 20140184611 (sending partial frame updates), Roh et al, U.S. Patent Publication No. 20140218378 (updating partial frame of image), Lee et al, U.S. Patent Publication No. 20140267329 (figures 2-3, 11), Woo et al, U.S. Patent Publication No. 20160329033 (display device), Kim et al, U.S. Patent Publication No. 20160343355 (display driving circuit), Singh et al, U.S. Patent Publication No. 20170109859 (partial refresh of display devices), Yoneda, U.S. Patent Publication No. 20170186365 (display device), Ansari et al, U.S. Patent Publication No. 20190043406 (partial frame updates), Kwa et al, U.S. Patent Publication No. 20190043458 (partial frame notifications), Sameer et al, U.S. Patent Publication No. 20250069539 (power optimized multi-regional update display).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dorothy H Harris whose telephone number is (571)270-7539. The examiner can normally be reached Monday - Friday 8am - 4pm.
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/Dorothy Harris/Primary Examiner, Art Unit 2625
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